Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.

An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin on the chip, and where the pin is adapted to be coupled to an external resistor, where the external resistor is external to the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first switch, and a second capacitor coupled to a second switch. The oscillator circuit includes leakage circuitry coupled to the current mirror, where the leakage circuitry is configured to draw a current from the current mirror proportional to a leakage current flowing through the external resistor from circuitry internal to the chip.

In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.

An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.