An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

An input sampling method includes the following: acquiring a first pulse signal and a second pulse signal respectively; widening a pulse width of the first pulse signal to obtain a widened first pulse signal; shielding an invalid signal in the second pulse signal based on the widened first pulse signal to obtain a to-be-sampled signal; and finally, sampling the to-be-sampled signal based on a clock signal. In this way, prior to signal sampling, the invalid signal is shielded to avoid additional power consumption caused by sampling the invalid signal, and at the same time, the pulse width of the signal is widened to avoid sampling failure.

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Provided is a booster circuit enabling improvement of efficiency of a stress test for a circuit to which a boosted voltage is applied. A voltage divider circuit is configured to have a voltage-dividing ratio that is variable depending on a test signal, and a limiter circuit is configured to clamp a voltage to a voltage higher than a boosted voltage in normal operation. In a test mode, the voltage divider circuit is controlled so that the boosted voltage becomes higher than that in the normal operation, and the limiter circuit clamps the boosted voltage, with the result that a booster section continuously operates.

A compensation circuit configured for coupling to a voltage source and a reference circuit. The voltage source is configured for supplying a supply voltage to the compensation circuit and the reference circuit. The reference circuit includes a first circuit node and a reference output electrically coupled to the first circuit node for outputting a reference signal having a constant reference amplitude. The compensation circuit includes a transient converter for converting a first transient perturbation of the supply voltage into a first compensation electrical signal proportional to said first transient perturbation, and an adder coupled to the transient converter for adding the first compensation electrical signal to an electrical signal at the first circuit node with a first polarity opposite to a disturbance polarity of a disturbance of the electrical signal in response to the first transient perturbation.

In an embodiment, a buffer circuit may includes a current source circuit, a self-bias generation circuit, a signal input circuit, and a first current sink circuit. The current source circuit may apply current to a first node and a second node in response to a self-bias voltage. The self-bias generation circuit may generate the self-bias voltage which has a voltage level between voltage levels of the first and second nodes. The signal input circuit may control the voltage levels of the first node and the second node in response to a first input signal and a second input signal. The first current sink circuit may control an amount of current flowing from the signal input circuit to a ground terminal in response to an enable signal and the self-bias voltage.

Provided are a switching regulator and a voltage-current conversion circuit configured to shorten a start-up period. The voltage-current conversion circuit includes: a first MOS transistor of a first conductivity type including a gate and a drain connected in common, and a source connected to a first power supply terminal; a first resistor connected between the drain of the first MOS transistor and a second power supply terminal; and a correction current generation unit including a second resistor, and configured to generate, as a correction current, through use of the second resistor, a current corresponding to a current generated when a voltage corresponding to an absolute value of a gate-source voltage of the first MOS transistor is applied to the first resistor. The voltage-current conversion circuit is configured to add the correction current to a current flowing through the first resistor, to thereby generate the conversion current.