A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit (14), a voltage-dividing resistor (16), a transistor switch (15), a zero-crossing detection circuit (19); the load power supply circuit (14) includes: a load (11), a diode (13), and an inductor (12); one end of the load power supply circuit (14) is connected with the operating voltage input terminal, the other end of the load power supply circuit (14) is connected with a first end of the transistor switch (15) and a first end of the voltage-dividing resistor (16), a second end of the voltage-dividing resistor (16) and a second end of the transistor switch (15) are connected with the ground, the load voltage is controlled by the transistor switch (15), the voltage-dividing terminal of the voltage-dividing resistor (16) is connected to a signal input terminal of the zero-crossing detection circuit (19), the zero-crossing detection circuit (19) is used to determine whether the current of the diode (13) crosses zero to obtain the on time of the diode (13), and the circuit for detecting load voltage uses the on time of the diode (13) and the on time of the transistor switch (15) to obtain the load voltage. The circuits are simple, but with high detection efficiency and low cost.

An integrated circuit can include latched comparator circuitry. The latched comparator circuitry may include first and second input transistors configured to receive an input signal, first and second cross-coupled inverting circuits, reset transistors, and a current pulse generator. The first and second inverting circuits may each include a pull-up transistor and a pull-down transistor. The first input transistor may be coupled between the pull-up and pull-down transistors in the first inverting circuit. The second input transistor may be coupled between the pull-up and pull-down transistors in the second inverting circuit. The reset transistors may be coupled in parallel with the pull-up transistors and may receive a clock signal. The current pulse generator may receive the clock signal and generate current pulse signals in response to detecting edges in the clock signal. Latched comparator circuitry configured and operated in this way can provide reduced clock kickback noise.

A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit, a voltage-dividing resistor, a transistor switch, a zero-crossing detection circuit; the load power supply circuit includes: a load, a diode, and a transformer; one end of a primary winding of the transformer is connected with the operating voltage input terminal, the other end of the primary winding of the transformer is connected with a first end of the transistor switch and a first end of the voltage-dividing resistor, a second end of the voltage-dividing resistor and a second end of the transistor switch are connected with the ground, the load voltage is controlled by the transistor switch.

A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit, a voltage-dividing resistor, a transistor switch, a zero-crossing detection circuit; the load power supply circuit includes: a load, a diode, and a transformer; one end of a primary winding of the transformer is connected with the operating voltage input terminal, the other end of the primary winding of the transformer is connected with a first end of the transistor switch and a first end of the voltage-dividing resistor, a second end of the voltage-dividing resistor and a second end of the transistor switch are connected with the ground, the load voltage is controlled by the transistor switch.

A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit (14), a voltage-dividing resistor (16), a transistor switch (15), a zero-crossing detection circuit (19); the load power supply circuit (14) includes: a load (11), a diode (13), and an inductor (12); one end of the load power supply circuit (14) is connected with the operating voltage input terminal, the other end of the load power supply circuit (14) is connected with a first end of the transistor switch (15) and a first end of the voltage-dividing resistor (16), a second end of the voltage-dividing resistor (16) and a second end of the transistor switch (15) are connected with the ground, the load voltage is controlled by the transistor switch (15), the voltage-dividing terminal of the voltage-dividing resistor (16) is connected to a signal input terminal of the zero-crossing detection circuit (19), the zero-crossing detection circuit (19) is used to determine whether the current of the diode (13) crosses zero to obtain the on time of the diode (13), and the circuit for detecting load voltage uses the on time of the diode (13) and the on time of the transistor switch (15) to obtain the load voltage. The circuits are simple, but with high detection efficiency and low cost.

A receiver circuit receives a differential signal that includes positive and negative spikes, and produces an output signal as a function of the differential signal. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses lasting longer than a threshold. The logic produces a set correction signal and a reset correction signal. The logic circuit produces a corrected set signal and a corrected reset signal. An output circuit produces an output signal based on the corrected set signal and the corrected reset signal.

The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

A receiver circuit receives a differential signal that includes positive and negative spikes, and produces an output signal as a function of the differential signal. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses lasting longer than a threshold. The logic produces a set correction signal and a reset correction signal. The logic circuit produces a corrected set signal and a corrected reset signal. An output circuit produces an output signal based on the corrected set signal and the corrected reset signal.

A receiver circuit receives a differential signal that includes positive and negative spikes, and produces an output signal as a function of the differential signal. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses lasting longer than a threshold. The logic produces a set correction signal and a reset correction signal. The logic circuit produces a corrected set signal and a corrected reset signal. An output circuit produces an output signal based on the corrected set signal and the corrected reset signal.