A preprocessing circuit for a comparator has a high voltage selection circuit, a first constant voltage circuit, a second constant voltage circuit, a first transistor, and a second transistor. The high voltage selection circuit receives a first voltage and a second voltage, and provides a selected voltage. The first constant voltage circuit provides a first clamping voltage based on the selected voltage, and the second constant voltage circuit provides a second clamping voltage based on the selected voltage. The first transistor receives the first voltage and the first clamping voltage, and provides a first comparison voltage to a first comparison terminal of the comparator. The second transistor receives the second voltage and the second clamping voltage, and provides a second comparison voltage to a second comparison terminal of the comparator.

The present invention provides a dynamic comparator including a dynamic amplifier and a latch circuit. The dynamic amplifier includes a first input pair, a current source and a gain boosting circuit. The first input pair is configured to receive an input signal to generate an amplified signal at an output terminal. The current source is coupled between the first input pair and a first reference voltage. The gain-boosting circuit is coupled between the first input pair and a second reference voltage, and is configured to receive the input signal to selectively inject current to the output terminal or sink current from the output terminal. The latch circuit is coupled to the dynamic amplifier, and is configured to receive the amplified signal to generate an output signal.

An envelope detector comprises a first differential transistor pair that receives first and second input signals, a second differential transistor pair that receives third and fourth input signals, a resistor, a current source, and a comparator. The first and second differential pairs each comprise two transistors having first current terminals coupled together and second current terminals coupled together. The resistor is coupled between the second current terminals of the first and second differential pairs. The current source has a first terminal coupled to the second terminal of the resistor and to second current terminals of the second differential pair and a second terminal configured to receive a negative supply voltage. The comparator has a negative input coupled to first current terminals of the first differential pair and a positive input coupled to first current terminals of the second differential pair.

A circuit includes a transistor input pair, a differential input having a comparator input, and a level shifter. The transistor input pair is adapted to be coupled between a voltage supply and a comparator output. The transistor input pair includes a first transistor having a gate and a drain. The drain of the first transistor is coupled to the comparator output. The level shifter is coupled between the transistor input pair and the differential input. The level shifter includes a second transistor having a gate and a source. The gate of the second transistor is coupled to the comparator input. The source of the second transistor is coupled to the gate of the first transistor.

A comparator may include: a comparison block suitable for comparing a ramp signal and a pixel signal, and outputting a comparison signal; a voltage adjusting block suitable for adjusting a clamping voltage; and an output voltage swing control block suitable for controlling an output voltage swing of the comparison block according to the clamping voltage from the voltage adjusting block.

The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

A semiconductor device includes a signal conversion circuit configured to convert a sensing current provided from a sensing element into a sensing voltage; an analog-to-digital converter (ADC) configured to convert the sensing voltage to a digital value; and a driving circuit configured to drive a light emitting element, wherein the ADC generates a digital value corresponding to proximity to an object by performing a primary operation comparing a ramp signal varying with time and the sensing voltage while the light emitting element is not driven and a secondary operation comparing the ramp signal and the sensing voltage while the light emitting element is driven.

A comparator includes a second-stage circuit, a first input circuit, a second input circuit, a first cross-coupled circuit and a second cross-coupled circuit. The first input circuit is configured to generate a first data terminal voltage and a first reference terminal voltage. The first cross-coupled circuit is configured to perform mutual positive feedback on the first data terminal voltage and the first reference terminal voltage to generate a first differential signal. The second input circuit is configured to generate a second data terminal voltage and a second reference terminal voltage. The second cross-coupled circuit is configured to perform mutual positive feedback on the second data terminal voltage and the second reference terminal voltage to generate a second differential signal. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

A comparator circuit with dynamic biasing comprises a comparator, first dynamic biasing generator, first extra biasing device, second dynamic biasing generator, and second extra biasing device. The comparator includes a biasing circuit, input stage, active loads, and output terminal. The input stage has a first input terminal, second input terminal, first current path, and second current path. The comparator is configured to output an output signal at the output terminal according to the first input signal and second input signal. The first dynamic biasing generator is coupled between a first detection node and the first extra biasing device coupled to the biasing circuit. The second dynamic biasing generator is coupled between a second detection node and the second extra biasing device coupled to the biasing circuit. The first and second detection nodes are between the input stage and the active loads.