A multi-ladder DAC includes first and second resistor ladders, with a switch-interconnect. The switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRswitch error, thereby improving DNL.

A frequency synthesizer is described that includes: a voltage controlled oscillator, VCO; a VCO bias circuit, operably coupled to the VCO and configured to provide a controllable bias current of the VCO; a temperature sensor, located in the frequency synthesizer, configured to determine an operating temperature of the frequency synthesizer; an analog-to-digital converter, ADC, operably coupled to the temperature sensor and configured to provide a digital representation of the determined operating temperature; and a bias control circuit operably coupled and configured to provide a bias control signal to the VCO bias circuit based on the determined operating temperature of the frequency synthesizer. The VCO bias circuit is configured to adjust the controllable bias current applied to the VCO based on the bias control signal.

A frequency synthesizer (230) is described that includes: a voltage controlled oscillator, VCO (330); a VCO bias circuit (370), operably coupled to the VCO (330) and configured to provide a controllable bias current (384) of the VCO (330); a temperature sensor (372) located in the frequency synthesizer (230) and configured to determine an operating temperature of the frequency synthesizer (230); an analog-to-digital converter, ADC (376), operably coupled to the temperature sensor (372) and configured to provide a digital representation (378) of the determined operating temperature; and a bias control circuit (380) operably coupled to the ADC (376) and the VCO bias circuit (370) and configured to provide a bias control signal (382) to the VCO bias circuit (370) based on the determined operating temperature of the frequency synthesizer (230). The VCO bias circuit (370) is configured to adjust the controllable bias current (384) applied to the VCO based on the bias control signal (382). The frequency synthesizer (230) includes a digitally-controlled bias current adjustment method for a wideband low noise VCO, for example using idle time intervals of signal transitions.

A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.

A novel and useful mm-wave frequency generation system is disclosed that takes advantage of injection locking techniques to generate an output oscillator signal with improved phase noise (PN) performance and power efficiency. Low frequency and high frequency DCOs as well as a pulse generator make up the oscillator system. A fundamental low frequency (e.g., 30 GHz) signal and its sufficiently strong higher (e.g., fifth) harmonic (e.g., 150 GHz) are generated simultaneously in a single oscillator system. The second high frequency DCO having normally poor phase noise is injected locked to the first low frequency DCO having good phase noise. Due to injection locking, the high frequency output signal generated by the second DCO exhibits good phase noise since the phase noise of the second DCO tracks that of the first DCO.

Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency stored in memory, and, based on the comparison, adjust frequency of the DUT generating the DUT input.

A novel and useful mm-wave frequency generation system is disclosed that takes advantage of injection locking techniques to generate an output oscillator signal with improved phase noise (PN) performance and power efficiency. Low frequency and high frequency DCOs as well as a pulse generator make up the oscillator system. A fundamental low frequency (e.g., 30 GHz) signal and its sufficiently strong higher (e.g., fifth) harmonic (e.g., 150 GHz) are generated simultaneously in a single oscillator system. The second high frequency DCO having normally poor phase noise is injected locked to the first low frequency DCO having good phase noise. Due to injection locking, the high frequency output signal generated by the second DCO exhibits good phase noise since the phase noise of the second DCO tracks that of the first DCO.

A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.

A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

In certain aspects, a system includes a voltage-controlled oscillator (VCO), a phase detector configured to receive a reference signal, a frequency divider coupled between an output of the VCO and the phase detector, a phase-to-current circuit coupled to an output of the phase detector, and a temperature circuit configured to output a temperature-dependent voltage. The system also includes a switching circuit configured to selectively couple the phase-to-current circuit to an input of the VCO and configured to selectively couple the temperature circuit to the input of the VCO.