A clock circuit constructed in a processor integrated circuit includes a phase lock loop PLL, a clock tree, and a clock grid. The clock tree includes a plurality of clock buffers in a layered structure, The clock tree is configured to receive a first clock signal clk_1 that is output by the phase lock loop PLL, and to output a second clock signal clk_2. A plurality of child node circuits (400) are disposed on some nodes of the clock grid, and are configured to generate a third clock signal clk_3 based on the second clock signal clk_2. The clock grid (330) and the clock tree (320) are distributed on multiple dies in a three-dimensional structure of the processor integrated circuit.

A method is provided for enhancing the detection of the start time of a reference oscillator (4) of a super-regenerative receiver (1), which includes the reference oscillator, a bias current generator (7), an oscillation detector (6), and an impedance matching unit (3). Following the supply of the bias current (i_vco) after receiving the activation control signal (Sosc), an oscillation detection is performed by the oscillation detector (6), and once oscillation is detected, an additional amplification current (iboost) dependent on the envelope of the detected oscillation, of an amplification current generation circuit is supplied to the reference oscillator (4) in addition to the bias current to amplify the oscillation signal to be above a critical oscillation start threshold so as to precisely define the start time of the oscillator, and enable the oscillation detector (6) to order the stoppage of oscillation of the reference oscillator (4).

A method for controlling a phase-locked loop circuit, can include: acquiring values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to desired values of a frequency control word signal and acquiring values of a charge pump current control signal respectively corresponding to the desired values of the frequency control word signal in a calibration mode, where the frequency control word signal characterizes a ratio of a desired locked frequency to a frequency of a reference signal; and determining a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the frequency control word signal in a phase-locked mode, in order to control the phase-locked loop circuit to achieve phase lock.

In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

Techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles are disclosed. Particularly, phased array architectures based on novel PLL-coupled phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are described. In one aspect, a phased array including an array of unit cells is disclosed. In some embodiments, each unit cell in the array of unit cells includes a dual-nested PLL that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell. Moreover, each PLL includes control circuitry that can generate a wide range of phase shifts between adjacent unit cells to facilitate phased-array operations. Note that using the dual-nested PLL to generate a desired phase shift between adjacent radiating elements eliminates the use of conventional lossy phase shifters in the phased array.

Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

A method is provided for enhancing the detection of the start time of a reference oscillator (4) of a super-regenerative receiver (1), which includes the reference oscillator, a bias current generator (7), an oscillation detector (6), and an impedance matching unit (3). Following the supply of the bias current (i_vco) after receiving the activation control signal (Sosc), an oscillation detection is performed by the oscillation detector (6), and once oscillation is detected, an additional amplification current (iboost) dependent on the envelope of the detected oscillation, of an amplification current generation circuit is supplied to the reference oscillator (4) in addition to the bias current to amplify the oscillation signal to be above a critical oscillation start threshold so as to precisely define the start time of the oscillator, and enable the oscillation detector (6) to order the stoppage of oscillation of the reference oscillator (4).

A method for controlling a phase-locked loop circuit, can include: acquiring values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to desired values of a frequency control word signal and acquiring values of a charge pump current control signal respectively corresponding to the desired values of the frequency control word signal in a calibration mode, where the frequency control word signal characterizes a ratio of a desired locked frequency to a frequency of a reference signal; and determining a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the frequency control word signal in a phase-locked mode, in order to control the phase-locked loop circuit to achieve phase lock.

The disclosure relates to technology for power supply for a voltage controller oscillator (VCO). A peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.

Techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles are disclosed. Particularly, phased array architectures based on novel PLL-coupled phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are described. In one aspect, a phased array including an array of unit cells is disclosed. In some embodiments, each unit cell in the array of unit cells includes a dual-nested PLL that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell. Moreover, each PLL includes control circuitry that can generate a wide range of phase shifts between adjacent unit cells to facilitate phased-array operations. Note that using the dual-nested PLL to generate a desired phase shift between adjacent radiating elements eliminates the use of conventional lossy phase shifters in the phased array.