A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.

A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL’s bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.

The present invention relates to a frequency modulation method based on a phase-locked loop capable of performing fast modulation independent of bandwidth. A frequency modulation system based on a phase-locked loop capable of performing fast modulation independent of bandwidth according to the present invention includes a loop filter including a proportional path and an integral path to determine a bandwidth of a phase-locked loop, a voltage-controlled oscillator configured to adjust a frequency according to an output of the loop filter, and a slope alternator configured to alternate an input current of the loop filter, wherein the slope alternator is located in the integral path of the loop filter to generate an offset current at a moment of change from a modulation rise to a modulation fall.

A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.