A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.

A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.

An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.

A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer. Such a cross-correlation reference signal can be used for cross-correlation with the electrical reception signal to improve the reception quality.

A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer. Such a cross-correlation reference signal can be used for cross-correlation with the electrical reception signal to improve the reception quality.

A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.

A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) to generate a multi-bit code based on a phase error between a reference clock and a feedback clock, a digital loop filter (DLF) coupled to the TDC, a digitally-controlled oscillator (DCO) circuit coupled to the DLF and to generate an output signal that is convertible to the feedback clock, and a logic component coupled to an input of the DCO circuit. The logic component is to: trigger, in response to detecting a power on of the DPLL circuit, a switch to decouple the DLF from the DCO circuit; determine, from the reference clock, a target frequency; measure a frequency of the feedback clock; and iteratively generate, based on the frequency during each iteration, a set of digital bits to the input of the DCO circuit that successively causes the frequency to converge towards the target frequency.

A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) to generate a multi-bit code based on a phase error between a reference clock and a feedback clock, a digital loop filter (DLF) coupled to the TDC, a digitally-controlled oscillator (DCO) circuit coupled to the DLF and to generate an output signal that is convertible to the feedback clock, and a logic component coupled to an input of the DCO circuit. The logic component is to: trigger, in response to detecting a power on of the DPLL circuit, a switch to decouple the DLF from the DCO circuit; determine, from the reference clock, a target frequency; measure a frequency of the feedback clock; and iteratively generate, based on the frequency during each iteration, a set of digital bits to the input of the DCO circuit that successively causes the frequency to converge towards the target frequency.

In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.

In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.