A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.

A device for synchronizing a periodic high frequency power signal (18) and an external reference signal (10). The device comprises a phase control circuit (100) and a digital oscillator circuit (130). The digital oscillator circuit (130) is connected to the phase control circuit (100). The digital oscillator circuit (130) comprises means for generating the periodic high frequency power signal (18) dependent on the control signal from the phase control circuit. The phase control circuit (100) is configured to determine a phase difference of the periodic high frequency power signal (18) and the external reference signal (10).

An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.

A control unit for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i) each having a respective output frequency (f.sub.i), phase (Φ.sub.i), and amplitude (A.sub.i), including a signal comparator configured to compare a reference signal having a reference frequency (f.sub.ref) and a reference phase (Φ.sub.ref) with a feedback signal having a feedback frequency (f.sub.PLL) and a feedback phase (Φ.sub.PLL), and configured to generate an error signal representative of a difference between the reference signal and the feedback signal; and a data processing unit receiving as an input signal the error signal generated by the signal comparator, and outputting a plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) as a function of the error signal; wherein a plurality of waveform generators (DDS.sub.PLL, DDS.sub.i) each receiving at least one of the plurality of waveform tuning signals (FTW.sub.PLL, FTW.sub.i) output by the data processing unit, wherein each waveform generator (DDS.sub.PLL, DDS.sub.i) generates a time-dependent amplitude signal (A.sub.PLL(t), A.sub.i(t)) as a function of the received respective waveform tuning signal (FTW.sub.PLL, FTW.sub.i), wherein one predetermined amplitude signal (A.sub.PLL(t)) of the generated plurality of amplitude signals (A.sub.PLL(t), A.sub.i(t)) represents the feedback signal input to the signal comparator, and the other amplitude signals (A.sub.i(t)) represent the respective radio frequency (RF) output signals (RF.sub.out,i) to be generated, and wherein the data processing unit is configured to adjust both the waveform tuning signal (FTW.sub.PLL) corresponding to the one predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal such as to minimize the error signal, and the other waveform tuning signals (FTW.sub.i) corresponding to the other amplitude signals (A.sub.i(t)) representing the radio frequency (RF) output signals (RF.sub.out,i) based on the adjusted waveform tuning signal (FTW.sub.PLL) of the predetermined amplitude signal (A.sub.PLL(t)) representing the feedback signal.

The disclosure further describes a radio frequency (RF) power generator, an arrangement of at least two such radio frequency (RF) power generators, and a method each for generating a plurality of synchronized radio frequency (RF) output signals (RF.sub.out,i).

Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A card include first transmit (Tx) component configured to connect to a second receive (Rx) component in a second card; a first Rx component configured to connect to a second Tx component in the second card; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to compensate for differences between i) the first Tx component and the second Rx component, and ii) the first Rx component and the second Tx component.

A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.