A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.

A device and method is presented to allow the high frequency clock generators and functional blocks of a wireless communication device to enter a very low power sleep state while the low frequency reference clock generator within the wireless communications device remains in an active state. The timing block provides methods of increasing and maintaining accuracy of the system timer which may have been reduced by temperature variation or manufacturing defects. The timing block also allows for selection of the highest accuracy clock from among multiple high frequency clock references. A device for timing control is presented comprising at least one high frequency reference clock, a low frequency reference clock and a timing controller for generating a system timer, wherein the timing controller selects one of the at least one high frequency reference clock and processes the low frequency reference clock with the selected high frequency reference clock.

A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.

The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.

A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.

In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.

A cross-clock-domain processing circuit configured to implement data processing between asynchronous clock domains with a relatively low latency. The cross-clock-domain processing circuit includes a jitter filtering circuit and a synchronization circuit. The jitter filtering circuit is configured to: perform jitter filtering on a clock recovered from input data; adjust a jitter-filtered clock phase; and output a processed input data clock as an output data clock to the synchronization circuit. The synchronization circuit is configured to perform cross-clock-domain synchronization on the input data based on the input data clock and the output data clock.

A cross-clock-domain processing circuit configured to implement data processing between asynchronous clock domains with a relatively low latency. The cross-clock-domain processing circuit includes a jitter filtering circuit and a synchronization circuit. The jitter filtering circuit is configured to: perform jitter filtering on a clock recovered from input data; adjust a jitter-filtered clock phase; and output a processed input data clock as an output data clock to the synchronization circuit. The synchronization circuit is configured to perform cross-clock-domain synchronization on the input data based on the input data clock and the output data clock.

A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix.