Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

A system includes a digital-to-analog converter comprising a plurality of unit elements, and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes a circuit configured to determine a number of unit elements of a digital-to-analog converter to be transitioned (N.sub.tm), determine a first number of unit elements to be turned on, and determine a second number of unit elements to be turned off. The circuit may further generate a first signal identifying individual unit elements of one or more unit elements of the digital-to-analog converter in the off state to be turned on, and a second signal identifying the individual unit elements of one or more unit elements of the digital-to-analog converter in the on state to be turned off.

A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.

An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

A DWA circuit includes: a thermometer conversion unit configured to convert an input digital signal into a thermometer code; a shift amount storage unit configured to store a shift amount; a shift unit configured to cyclically shift the thermometer code; an arrangement conversion unit configured to supply, to an analog output circuit, an output control code obtained by converting a bit arrangement of a shifted code; and an update unit configured to update the shift amount, in which the shifted code includes a plurality of unconverted bit fields, the output control code includes a plurality of converted bit fields, and the arrangement conversion unit is configured to perform arrangement conversions on a plurality of bits having a same position in a bit field in the plurality of unconverted bit fields, to arrange the plurality of bits in a same converted bit field among the plurality of converted bit fields.

A data converter is disclosed. The data converter includes a loop-filter, a quantizer, an analog dynamic element matching (DEM) shuffler, a digital DEM shuffler and a feedback digital-to-analog converter. The loop-filter receives analog signals from an analog input. The quantizer then converts the filtered analog signals from the loop-filter to digital signals at a digital output. The analog DEM shuffler shuffles a set of analog threshold levels of the quantizer to yield a set of partially shuffled digital data at an output of the quantizer. The digital DEM shuffler shuffles the set of partially shuffled digital data from the output of the quantizer to yield a set of shuffled digital data. The feedback digital-to-analog converter converts the set of shuffled digital data to a set of analog data to be fed back to the loop-filter.

The present disclosure provides an output conversion circuit and a fingerprint identification system. The output conversion circuit includes: a comparator, a counter, and a reference signal generator, where the comparator includes: a first input end, configured to receive a first output signal; a second input end; and an output end, configured to generate a comparison output signal; the counter is connected to the output end of the comparator, and configured to generate a second output signal; and the reference signal generator is connected to the second input end, and configured to generate a reference signal, where the reference signal generator includes a random digit generator configured to generate a random digit, and the reference signal is associated with the random digit; where the comparator generates the comparison output signal according to the first output signal and the reference signal.

An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.