A rollable display device includes a rollable display and a first protection film disposed on a first surface of the rollable display. The first protection film extends beyond a first display edge of the rollable display. The rollable display device further includes a second protection film disposed on a second surface of the rollable display facing the first surface of the rollable display. The second protection film extends beyond the first display edge of the rollable display. The rollable display device additionally includes a first adhesive layer disposed between the rollable display and the first protection film. The rollable display device further includes second adhesive layer disposed between the rollable display and the second protection film, and a first adhesion part disposed adjacent to the first display edge of the rollable display and between the first protection film and the second protection film.

A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

A SAR ADC (50) is disclosed. It comprises a differential input port having a first input (V.sub.inP) configured to receive a first input voltage and a second input (V.sub.inN) configured to receive a second input voltage, of opposite polarity compared with first input voltage. Furthermore, it comprises a (300) having a first sub circuit (310P) comprising a first plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320P) of the first sub circuit (310P) with a first terminal, and a second sub circuit (310N) comprising a second plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320N) of the second sub circuit (310N) with a first terminal. For each capacitor (2C.sub.u, C.sub.u) of the first plurality of capacitors, the first sub circuit (310P) comprises a first switch (S4) connected between the first input (V.sub.inP) of the SAR ADC and a second terminal of that capacitor, a second switch (S.sub.2) connected between a first reference-voltage input (V.sub.rP) and the second terminal of that capacitor, a third switch (S.sub.1) connected between a second reference-voltage input (V.sub.rN) and the second terminal of that capacitor, and a capacitive device (X.sub.P) connected between the second input (V.sub.inN) of the SAR ADC and the second terminal of that capacitor. The second sub circuit is arranged in a similar way.

An analog input device, which converts an inputted analog signal to a digital signal and outputs the digital signal, includes a high resolution AD converter, a first low resolution AD converter, and a second low resolution AD converter. When a difference between a first digital signal converted by the high resolution AD converter and a second digital signal converted by the first low resolution AD converter is equal to or less than a predetermined first threshold, the analog input device outputs first digital signal. When the difference between the first digital signal and the second digital signal is larger than the predetermined first threshold, the analog input device stops an output of the first digital signal.

Analogue-to-digital converter, ADC, circuitry comprising: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry comprising at least one compensation capacitor and configured, in a precharge operation prior to the subconversion operation, to connect the at least one compensation capacitor so that the at least one compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the at least one compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry compensates for the charge drawn from the first voltage reference, REF1, by the successive-approximation circuitry.

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

An apparatus configured to transmit and receive a radio frequency (RF) signal is provided. The apparatus includes a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal, a power amplifier configured to amplify the analog signal, and an antenna configured to output, as the RF signal, the amplified analog signal to the outside. The DAC includes a current cell matrix including a plurality of current cells configured to generate the analog signal, a plurality of normal paths configured to control the plurality of current cells to be turned on or off, based on the digital signal, and a plurality of alternative paths configured to selectively consume power, based on a pattern of the digital signal.

A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.

A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.

A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.