Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.

An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

An AD conversion circuit provided in a solid-state image sensor includes a counter circuit that performs count processing and a first latch circuit that holds at least one of a discrimination result of a first comparison circuit and a first output result of the counter circuit.

This disclosure describes techniques for transferring data from an analog-to-digital converter (ADC) to a host device. The techniques may determine whether an ADC is operating in a quiet conversion time period, and selectively deactivate a digital data output of the ADC when the ADC is operating in the quiet conversion time period. This may allow an ADC to transfer data during both the conversion and acquisition phases of the ADC (rather than just during the acquisition phase), thereby increasing the data throughput of the ADC for a given transfer clock speed. The techniques may further allow data to be transferred during the conversion phase of an ADC without requiring a host device to be aware of the quiet conversion time period requirements of the ADC. In this way, the data throughput of an ADC data transfer may be increased with relatively little additional complexity added to a host device.

A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

A hybrid comparator includes an analog signal combiner and a dynamic latch. The analog signal combiner is configured to receive an input analog signal and an input reference signal, and generate an analog output signal by combining the input analog signal and the input reference signal. The dynamic latch is configured to receive the analog output signal and a clock signal, and generate a digital output signal.

An AD conversion circuit provided in a solid-state image sensor includes a counter circuit that performs count processing and a first latch circuit that holds at least one of a discrimination result of a first comparison circuit and a first output result of the counter circuit.

To simplify the circuit configuration and design of an analog-digital converter. A low-order bit latch section latches, as low-order bits, Gray code data corresponding to a reference clock by using, as a trigger, inversion of an output of a comparator. A high-order bit counter section counts one or both of edges of a CNT signal corresponding to the reference clock and stops a count of high-order bits by using, as a trigger, inversion of an output of the comparator.

The present disclosure provides an analogue to digital converter (ADC) (100), which includes: a capacitive digital to analogue converter (DAC) (120) configured to sample and hold a received sampling input signal and a latched comparator (140) including a first metal oxide semiconductor field effect transistor (MOSFET) (202); a second MOSFET (204) connected in parallel to the first MOSFET; a third MOSFET (226), wherein a third source terminal of the third MOSFET (226) is coupled with first drain terminal and second drain terminal of the first and second MOSFET (202, 204), wherein a sampling switch (130) is configured to the third source terminal to selectively allow voltage to be supplied to the third MOSFET (226), and wherein the sampling switch is configured to disallow voltage to be supplied to the third MOSFET when the ADC is sampling the input signal.

To simplify the circuit configuration and design of an analog-digital converter. A low-order bit latch section latches, as low-order bits, Gray code data corresponding to a reference clock by using, as a trigger, inversion of an output of a comparator. A high-order bit counter section counts one or both of edges of a CNT signal corresponding to the reference clock and stops a count of high-order bits by using, as a trigger, inversion of an output of the comparator.