Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes an input port, a non-binary DAC, an ADC to receive an output of the non-binary DAC, a lookup table to store a plurality of calibration code and a calibration logic coupled with the non-binary DAC. The self-calibrating DAC has two modes of operations, a calibration mode and a normal operational mode. In the calibration mode, the self-calibrating DAC is configured to calculate weightages of the non-binary DAC and to calculate an offset coefficient and a gain coefficients using high precision on chip analog-to-digital converter (ADC).

Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.

Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

In accordance with various embodiments of the disclosed subject matter, a system, device, apparatus and method for calibrating a split bit digital readout to avoid misalignment of the least significant counter bit (i.e., the LSB of the M most significant bits) and most significant residual bit (i.e. the MSB of the N least significant bits). For example, various embodiments provide a field programmable gate array (FPGA), digital signal processing (DSP) function and the like configured to calibrate one or many split bit digital readouts such as may exist on a digital pixel sensor (DPS) or other device.

An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component. Thereafter, a time-offset and gain estimator component can determine one of gain error calibration data or time-offset calibration data based at least in part on an output signal of the conversion component, which can be stored and/or used to calibrate individual time-interleaved ADCs.