A mobile telecommunication wireless repeater includes: a combination stage for combining a received signal with a feedback cancellation signal; a comparison stage for comparing an input signal of the combination stage with an output signal of the combination stage and determining a weighted value and a time offset value for a feedback signal to be cancelled, based on the comparison; and a recombination stage comprising one or more adaptive filters and configured to receive the weighted value and the time offset value and generate the feedback cancellation signal according to the weighted value and the time offset value.

An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.

Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component. Thereafter, a time-offset and gain estimator component can determine one of gain error calibration data or time-offset calibration data based at least in part on an output signal of the conversion component, which can be stored and/or used to calibrate individual time-interleaved ADCs.

Each realization of an electric circuit design defines a frequency response. For a test lot of the design, frequency responses are measured, each at a stable value of an environment parameter, wherein the totality of the values are distributed over a parameter range. Based on the measurements, a design-specific model is defined that describes a frequency response of the design in dependence of the environment parameter. For a unit in a main lot of realizations of the design, a unit-specific frequency response is measured at a stable value of the environment parameter; the model is fitted to the response, whereby a unit-specific model is obtained; data representing the unit-specific model is stored in association with the unit; and the unit is operated in conjunction with a compensation stage configured to determine a present value of the environment parameter and compensate drift in relation to a parameter-independent reference frequency response.

A delta-sigma modulator. The delta-sigma modulator includes a loop filter (LF) and a digital-to-analog converter (DAC) connected to an input of the LF. The delta-sigma modulator also includes an asynchronous successive-approximation register (ASAR) quantizer (QTZ) connected to the DAC. The delta-sigma modulator also includes a second order noise coupling circuit (NC) connected to the ASAR and the DAC.

Each realization of an electric circuit design defines a frequency response. For a test lot of the design, frequency responses are measured, each at a stable value of an environment parameter, wherein the totality of the values are distributed over a parameter range. Based on the measurements, a design-specific model is defined that describes a frequency response of the design in dependence of the environment parameter. For a unit in a main lot of realizations of the design, a unit-specific frequency response is measured at a stable value of the environment parameter; the model is fitted to the response, whereby a unit-specific model is obtained; data representing the unit-specific model is stored in association with the unit; and the unit is operated in conjunction with a compensation stage configured to determine a present value of the environment parameter and compensate drift in relation to a parameter-independent reference frequency response.

A test and measurement instrument including a splitter configured to split an input signal into at least two split signals, at least two harmonic mixers configured to mix an associated split signal with an associated harmonic signal to generate an associated mixed signal, at least two digitizers configured to digitize the associated mixed signal, at least two MIMO polyphase filter arrays configured to filter the associated digitized mixed signal of an associated digitizer of the at least two digitizers, at least two pairs of band separation filters configured to receive the associated digitized mixed signals from each of the MIMO polyphase filter arrays and output a low band of the input signal and a high band of the input signal based on a time different between the at least two digitizers and a phase drift of a local oscillator, and a combiner configured to combine the low band of the input signal and the high band of the input signal to form a reconstructed input signal.

Various techniques that can provide a capability to background calibrate ADC linearity error, e.g., due to capacitor mismatch drift and other parameter drift, during normal ADC operation in which analog-to-digital signal conversions are ongoing. A method can include grouping capacitors of an ADC into multiple clusters and calibrating under an arbitrary signal condition. To quickly converge the calibration result, the same arbitrary signal can be converted twice, and the capacitor(s) being calibrated can be modulated after first conversion. The difference between the results of the first and second conversions can contain the error information that can be used for calibration, and the signal component can be removed by this process. These techniques can provide improved linearity at 20-bit level and beyond.

An interleaved Analog-to-Digital Converter (ADC) has a reference channel receiving an attenuated analog input. The reference channel is also calibrated to remove capacitor-ratio mismatch, static, and dynamic mismatches and produces a linear replica of the data channels with negligible nonlinear errors due to attenuation. Nonlinear errors on the data channels are corrected by Harmonic Distortion HD2 and HD3 coefficients. A counter increments when the sign bit of a nonlinear-corrected channel code is negative. The count is doubled and reduced by a number of samples to generate a HD2 cost function that adjusts the HD2 coefficient in a LMS loop. A HD3 correlation is generated by multiplying the reference channel output by its difference with the nonlinear-corrected channel code. The sign of the correlation code increments a second counter which generates a HD3 cost function whose sign bit adjusts the HD3 coefficient. These 2 counters generate cost functions, eliminating sample storage.

Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).