A voltage regulator circuit included in a computer system may include multiple phase circuits each coupled to a regulated power supply node via a corresponding inductor. The phase circuits may modify a voltage level of the regulated power supply node using respective control signals generated by a digital control circuit that processes multiple data bits. An analog-to-digital converter circuit may compare the voltage level of the regulated power supply node to multiple reference voltage levels and sample the resultant comparisons to generate the multiple data bits.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

An analog-to-digital converter (ADC) for converting an analog signal into a digital signal includes an amplifier circuit configured to receive the analog signal, and to generate a plurality of amplifier signals by amplifying the analog signal; a comparison circuit configured to compare a plurality of voltage levels corresponding to the plurality of amplifier signals with a positive reference voltage level and a negative reference voltage level, and to output conversion target signals based on a result of the comparison; and a converter circuit configured to convert the conversion target signals into a plurality of digital signals.

An apparatus configured to convert an analog input signal into a digital output signal may include a first amplification circuit configured to receive the analog input signal and a plurality of reference voltages and amplify differences between the analog input signal and the plurality of reference voltages; a plurality of first capacitors configured to respectively store charges corresponding to signals outputted by the first amplification circuit; a second amplification circuit configured to amplify differences among voltages of the plurality of first capacitors; a plurality of second capacitors configured to respectively store charges corresponding to signals outputted by the second amplification circuit; and a comparison circuit configured to generate the digital output signal by comparing voltages of the plurality of second capacitors with each other.

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.

Methods of performing mixed-signal/analog multiply-accumulate (MAC) operations used for matrix multiplication in fully connected artificial neural networks in integrated circuits (IC) are described in this disclosure having traits such as: (1) inherently fast and efficient for approximate computing due to current-mode signal processing where summation is performed by simply coupling wires, (2) free from noisy and power hungry clocks with asynchronous fully-connected operations, (3) saving on silicon area and power consumption for requiring neither any data-converters nor any memory for intermediate activation signals, (4) reduced dynamic power consumption due to Compute-In-Memory operations, (5) avoiding over-flow conditions along key signals paths and lowering power consumption by training MACs in neural networks in such a manner that the population and or combinations of multi-quadrant activation signals and multi-quadrant weight signals follow a programmable statistical distribution profile, (6) programmable current consumption versus degree of precision/approximate computing, (7) suitable for ‘always-on’ operations and capable of ‘self power-off’, (8) inherently simple arrangement for non-linear activation operations such as Rectified Linear Unit, ReLu, and (9) manufacturable on main-stream, low cost, and lagging edge standard digital CMOS process requiring neither any resistors nor any capacitors.

An analog-to-digital converter is disclosed that converts an input analog potential to a digital conversion value. An analog-to-digital converter according to one or more embodiments may include a comparator that compares the input analog potential with a reference potential; and a conversion circuit that measures comparison operation time from a start to an end of a comparison operation by the comparator and outputs the digital conversion value according to the measured comparison operation time and a comparison result by the comparator.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

A voltage regulator circuit included in a computer system may include multiple phase circuits coupled to a regulated power supply line via corresponding one of multiple inductors. The phase circuits may modify a voltage level of the regulated power supply line using respective control signals generated by a digital control circuit that processes multiple data bits. An analog-to-digital converter circuit may compare the voltage level of the regulated power supply node to multiple reference voltage levels and sample the resultant comparisons to generate the multiple data bits.