An imager device includes a pixel sensor configured to receive and convert incident radiation into a pixel signal and a readout circuit configured to receive the pixel signal from the pixel sensor, generate a received signal strength indicator (RSSI) value based on the pixel signal, and generate a digital signal based on the RSSI value and the pixel signal.

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

An integrated circuit (IC) includes an analog to digital converter (ADC) circuit having an ADC input and an ADC output. The ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal. An ADC circuit path is coupled between the ADC input and the ADC output. The ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path. The ADC has a reconfigurable resolution and a reconfigurable sampling rate. The ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.

Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

An analog-to-digital (ADC) circuit is disclosed that includes a first stage, a first amplifier, and a second amplifier. The first stage includes signal processing circuitry, and is configured to receive a differential input signal and generate a differential residue voltage signal on differential output nodes of the first stage. The first amplifier includes first amplifier circuitry. The first amplifier is electrically connected to the differential output nodes of the first stage, and configured to receive the differential residue voltage signal, and generate a first differential voltage signal from the differential residue voltage signal. The second amplifier includes second amplifier circuitry. The second amplifier is electrically connected to differential output nodes of the first amplifier, and configured to receive the first differential voltage signal, and generate a second differential voltage signal from the first differential voltage signal.

An integrated circuit (IC) includes an analog to digital converter (ADC) circuit having an ADC input and an ADC output. The ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal. An ADC circuit path is coupled between the ADC input and the ADC output. The ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path. The ADC has a reconfigurable resolution and a reconfigurable sampling rate. The ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.

A touch processing circuit includes: a front-end circuit including an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches each having two ends that are selectively connected each other, the front-end circuit being configured to process an input signal varying according to a touch; and a controller controlling the plurality of switches so that the front-end circuit is configured as a first circuit that accumulates deviation of the input signal between a first phase and a second phase during an integration period and a second circuit that converts the accumulated deviation into a digital signal during a conversion period.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

A touch processing circuit includes: a front-end circuit including an amplifier, a first capacitor, a second capacitor, a third capacitor, and a plurality of switches each having two ends that are selectively connected each other, the front-end circuit being configured to process an input signal varying according to a touch; and a controller controlling the plurality of switches so that the front-end circuit is configured as a first circuit that accumulates deviation of the input signal between a first phase and a second phase during an integration period and a second circuit that converts the accumulated deviation into a digital signal during a conversion period.