A semiconductor device with reduced power consumption can be provided. The semiconductor device includes a first transistor and a second transistor. The first transistor is a p-channel transistor including silicon in a channel formation region and the second transistor is an n-channel transistor including a metal oxide in a channel formation region. The metal oxide includes indium, an element M (e.g., gallium), and zinc. A gate of the first transistor is electrically connected to a gate of the second transistor, and one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The first transistor and the second transistor can each operate in a subthreshold region.

Aspects of the technology described herein relate to control circuitry configured to turn on and off the ADC driver. In some embodiments, the control circuitry is configured to turn on and off the ADC driver in synchronization with sampling activity of an ADC, in particular based on when an ADC is sampling. The control circuitry may be configured to turn on the ADC driver during the hold phase of the ADC a time period before the track phase and to turn off the ADC driver during the hold phase a time period after the track phase. In some embodiments, the control circuitry is configured to control a duty cycle of the ADC driver turning on and off. In some embodiments, the control circuitry is configured to control a ratio between an off current and an on current in the ADC driver.

An ADC device includes a DAC circuit, a comparator circuit, a SAR decision circuit, an oscillator circuit having a delay unit, and a processing circuit. The oscillator circuit is used for generating the clock signal according to a reset signal and a delay of the delay unit. The processing circuit is used for sequentially generating multiple bit conversion signals associated with multiple different bits of the decision signal, for generating at least one guard signal which follows the multiple bit conversion signals, and then for comparing the at least one guard signal with the reset signal to adjust the delay generated by the delay unit of the oscillator circuit.

A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.

A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

A batteryless wireless sensor system includes a data acquisition system, a radio frequency (RF) transceiver, and a batteryless wireless sensor device. The RF transceiver is in communication with the data acquisition system, transmits a RF signal, and receives sensor data and provide the sensor data to the data acquisition system. The batteryless wireless sensor device includes a RF transmitter, an analog to digital converter (ADC), and a sensor. The batteryless wireless sensor harvests energy from the RF signal and generates a DC signal based on the energy harvested from the RF signal, powers up and operates the ADC and the sensor based on the DC signal, and generates sensor data. The batteryless wireless sensor then transmits the sensor data via the RF transmitter to the RF transceiver. In certain examples, the ADC is implemented as a current mode ADC.

A batteryless wireless sensor system includes a data acquisition system, a radio frequency (RF) transceiver, and a batteryless wireless sensor device. The RF transceiver is in communication with the data acquisition system, transmits a RF signal, and receives sensor data and provide the sensor data to the data acquisition system. The batteryless wireless sensor device includes a RF transmitter, an analog to digital converter (ADC), and a sensor. The batteryless wireless sensor harvests energy from the RF signal and generates a DC signal based on the energy harvested from the RF signal, powers up and operates the ADC and the sensor based on the DC signal, and generates sensor data. The batteryless wireless sensor then transmits the sensor data via the RF transmitter to the RF transceiver. In certain examples, the ADC is implemented as a current mode ADC.

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator, a threshold generator and a controller. The comparator receives an analog signal and the SAR ADC outputs an output codeword. The comparator performs a plurality of first comparisons and a plurality of second comparisons. The controller determines a plurality of most significant bits of the output codeword according to a plurality of first comparison results corresponding to the first comparisons. The first comparisons are performed by comparing the analog signal with a plurality of first thresholds. The controller determines a plurality of least significant bits of the output codeword according to a plurality of second comparison results corresponding to the second comparisons. The second comparisons are performed by comparing the analog signal with a second threshold. The controller controls the threshold generator to produce the plurality of first thresholds and the second threshold according to the first comparison results.