A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.

A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. A number of capacitive digital analog converter (CDAC) cells of a power amplifier can be sized to provide defined power signals along a signal path. In response to an optimization component that is coupled to a CDAC cell of the plurality of CDAC cells operating in a high efficiency enable mode and the CDAC cell being powered off in an off mode, the optimization component can increase a power efficiency of the power amplifier by reducing an impedance of an output capacitor of the CDAC cell.

According to one embodiment, in a semiconductor integrated circuit, the plurality of storage devices are arranged in a form of a plurality of rows. Each of the storage devices are configured to store a bit position value of a weight of multiple bits. The plurality of multiplication circuits are arranged in a form of a plurality of rows and are configured to multiply a plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results. The one or more capacitive devices are configured to accumulate charges corresponding to the plurality of multiplication results. The adder circuit are configured to generate an output voltage corresponding to the total value of the charges accumulated in the one or more capacitive devices. The plurality of input voltages have different amplitudes. Each of the input voltages is associated with a corresponding bit position of the weight.

Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.

A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.