An operational amplifier includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.

Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

A digital-to-analog converter is provided. The digital-to-analog converter comprises a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter comprises a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells comprise different numbers of inverter cells. The digital-to-analog converter additionally comprises an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

A single-ended analog signal receiver apparatus is provided, which can cope with an external ground current and an undefined impedance through an AC bootstrap input impedance, while considering electromagnetic compatibility, convert a received single-ended analog signal into a balanced output differential signal, and may provide at a post-stage circuit output an output signal with lower noise through common mode rejection.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.