The present invention provides a probability mass redistributor device comprising an input port and an output port. The device comprises a mapping block configured to perform a selected mapping function from a plurality of mapping functions on a random bitstream to generate an output signal having a desired probability mass function, at least one difference block, wherein the input to the at least one difference block comprises the output from the mapping block, and the output of the at least one difference block produces a modulation term, and wherein the output of each difference block is the difference between a previous value of the input signal to the block and a current value of the input signal to the block, and a summing block for summing a signal received by the input port and the modulation term to form an output signal.

An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.

The present invention provides a probability mass redistributor device comprising an input port and an output port. The device comprises a mapping block configured to perform a selected mapping function from a plurality of mapping functions on a random bitstream to generate an output signal having a desired probability mass function, at least one difference block, wherein the input to the at least one difference block comprises the output from the mapping block, and the output of the at least one difference block produces a modulation term, and wherein the output of each difference block is the difference between a previous value of the input signal to the block and a current value of the input signal to the block, and a summing block for summing a signal received by the input port and the modulation term to form an output signal.

Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.

A sigma-delta modulator including at least first and second sub-modulators, each including an analog integration circuit, the analog integration circuit of the first sub-modulator having an output node connected to an input node of the analog integration circuit of the second sub-modulator, the modulator further comprising a coupling capacitor having a first electrode connected to an output node of the analog integration circuit of the second sub-modulator, and a comparator having its input coupled to the first electrode of the coupling capacitor by a first switch and to a second electrode of the coupling capacitor by a second switch.

Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a bandpass noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The bandpass noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.

An audio D/A converter includes: a first segment D/A converter including N elements; a second segment D/A converter including N elements; a first oversampling filter configured to process a PCM signal; a second oversampling filter configured to process a PCM signal; a first multilevel modulator configured to process an output of the first oversampling filter; a second multilevel modulator configured to process an output of the second oversampling filter; a first switching controller configured to control the first segment D/A converter according to an input to the first switching controller; and a second switching controller configured to control the second segment D/A converter according to an input to the second switching controller.