Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.

An integrator includes a first switch, a first capacitor, a second switch, a second capacitor, an amplifier, a third switch, a forth switch, a third capacitor, and a control circuit. The control circuit repeats a first phase and a second phase. In the first phase, the control circuit renders the first switch and the third switch to turn on and the second switch and the fourth switch to turn off. In the second phase, the control circuit renders the second switch and the fourth switch to turn on and the first switch and the third switch to turn off.

Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a comparison circuit, a control circuit, a digital-to-analog (D/A) conversion circuit, a switched buffer and a loop filter. The track-and-hold circuit is configured to output a first signal based on an input signal or a first timing signal. The comparison circuit is configured to generate a comparison result based on the first signal and a filtered residue signal. The control circuit is coupled to the comparison circuit, and is configured to generate an N-bit logical signal according to N comparison results from the comparison circuit. The D/A circuit is configured to generate a feedback signal based on the N-bit logical signal. The switched buffer is configured to generate a first error signal based on a second timing signal and a second error signal. The loop filter is configured to generate the filtered residue signal based on the first error signal.

The present application discloses a successive approximation register analog-to-digital converter with passive noise shaping, which comprises: switch capacitor arrays for acquiring analog input signals; a noise shaping circuit which is a passive integral network, the network has input ends connected respectively with output ends of the two switch capacitor arrays and for acquiring output signals of the two switch capacitor arrays, is composed of a plurality of sub passive integrators, and reconfigures the plurality of sub passive integrators to different circuit forms; a comparator which has two input ends connected respectively with output ends of the passive integral network and an output end connected with an input end of a logic circuit, and is configured to compare magnitudes of the output signals of the noise shaping circuit.

An analog-to-digital converter includes: a sample/hold circuit, which samples an analog signal, and outputs a first voltage; a digital-to-analog conversion circuit, which converts a digital signal to output a second voltage; an amplifier, which amplifies the first voltage and the second voltage; a noise shaping filter, which integrates a residual voltage corresponding to a difference between the amplified first voltage and the amplified second voltage, and generates a first integration voltage and a second integration voltage; a comparator, which compares a sum of the amplified first voltage, the first integration voltage, and the second integration voltage with the amplified second voltage; and a SAR logic, which outputs the digital signal according to a comparison result of the comparator, and controls the digital-to-analog conversion circuit.

A comparator compares a differential voltage between a voltage to be converted as an analog input voltage and a comparative voltage generated by a D/A converting unit with a comparison reference voltage. A switching circuit selectively connects a capacitor, associated with the analog input voltage selected as the voltage to be converted, to an output terminal of an integrator. The integrator integrates the differential voltage in a state where an A/D converting section has performed conversion operation on a least significant bit. A comparison reference voltage generating unit uses, as the comparison reference voltage, a charge voltage for the capacitor associated with the analog input voltage selected as the voltage to be converted.

Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.

An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold.