A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.

A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.

A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.

A microphone assembly includes a transducer element and a processing circuit. The processing circuit includes an analog-to-digital converter (ADC) configured to receive, sample and quantize a microphone signal generated by the transducer element to generate a corresponding digital microphone signal. The processing circuit includes a feedback path including a digital loop filter configured to receive and filter the digital microphone signal to provide a first digital feedback signal and a digital-to-analog converter (DAC) configured to convert the first digital feedback signal into a corresponding analog feedback signal. The processing circuit additionally includes a summing node at the transducer output configured to combine the microphone signal and the analog feedback signal.

A class-D amplifier includes measurement of speaker current via the low-side drive transistors of the amplifier. In one embodiment, a class-D amplifier includes two high-side transistors, two low-side transistors, a first sense resistor, a second sense resistor, and a sigma delta analog to digital converter (σΔ ADC). The two high-side transistors and two low-side transistors are connected as a bridge to drive a bridge tied speaker. The first sense resistor is connected between a first of the low-side transistors and a low-side reference voltage. The second sense resistor is connected between a second of the low-side transistors and the low-side reference voltage. The ΣΔ ADC is coupled to the bridge to measure voltage across the first sense resistor and the second sense resistor.

A semiconductor device such as a sigma delta A/D converter comprises an integrator configured to output first and second output signals, a quantizer configured to generate a first digital signal based on the output signals, first and second switches configured to control application of first and second reference voltages to a first resistor based on respective first and second control signals, and a third switch configured to control connection between the first resistor and a first input terminal of the integrator based on a third control signal. The first through third control signals are generated based on the first digital signal and a second digital signal obtained by delaying the first digital signal. The third switch is turned on when any one of the first and second switches is turned on, and is turned off when both the first and second switches are turned off.

LED drive control circuitry according to one embodiment outputs an LED drive control signal serving as driving a light emitting diode included in a photocoupler that performs insulation communication in synchronization with a reference clock signal. The LED drive control circuit includes a duty cycle changer that changes a duty cycle of the LED drive control signal in accordance with the reference clock signal and a signal synchronized with the reference clock signal.

An amplifier circuit includes a resistor divider (R.sub.REF) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d.sub.1, d.sub.2), resistor nodes (q) defined between adjacent resistive elements, and an input current source (I.sub.REF) connected or connectable to the first main node (a). The resistor divider (R.sub.REF) comprises two arrays of addressable switch elements controllable by a feedback signal (s.sub.FB) to be open or closed. The amplifier circuit includes a differential pair of transistors (T.sub.1, T.sub.2), wherein source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second node (b), gate terminals of the transistors (T.sub.1, T.sub.2) are connected to input signals (v.sub.1, v.sub.2), drain terminals of the transistors (T.sub.1, T.sub.2) are connected to current sources (I.sub.1, I.sub.2), and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the readout nodes (d.sub.1, d.sub.2). The amplifier circuit functions as a difference amplifier, wherein the bulk terminals affect a threshold of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

A driving circuit for controlling a MEMS oscillator includes a digital conversion stage to acquire a differential sensing signal indicative of a displacement of a movable mass of the MEMS oscillator, and to convert the differential sensing signal of analog type into a digital differential signal of digital type. Processing circuitry is configured to generate a digital control signal of digital type as a function of the comparison between the digital differential signal and a differential reference signal indicative of a target amplitude of oscillation of the movable mass which causes the resonance of the MEMS oscillator. An analog conversion stage includes a ΣΔ DAC and is configured to convert the digital control signal into a PDM control signal of analog type. A filtering stage of low-pass type, by filtering the PDM control signal, generates a control signal for controlling the amplitude of oscillation of the movable mass.