Patent classifications
H04J3/0688
MULTIPLE AND CASCADED REDUNDANT DISCIPLINED OSCILLATOR SYSTEMS IN A SPOOFING RESISTANT REFERENCE TIME SOURCE SYSTEM AND METHODS THEREOF
A system, non-transitory computer readable medium, and method include entering redundant oscillators and a cascaded oscillator of a spoofing resistant system into an initialization state. All but one of the redundant oscillators are disciplined to a time-and-frequency external input into normal disciplining state with the remaining one of the redundant oscillators in a holdover state. When all but one of the redundant oscillators have reached the normal disciplining state, placing all but one of the redundant oscillators into the holdover state, disciplining the remaining one of the redundant oscillators to the time and frequency external input, and disciplining the cascaded oscillator to one of the all but one of the redundant oscillators now in the holdover state. When the remaining one of the redundant oscillators and the cascaded oscillator have reached the normal disciplining state, transitioning from an initialization stage to a steady state management stage.
Fault-tolerant time server for a real-time computer sytem
The invention relates to a method for providing a fault-tolerant global time via a time server in a distributed real-time computer system, wherein the time server comprises four components which are connected to one another via a bi-directional communication channel. At a priori defined periodic, internal synchronization times, each of the four components transmits an internal synchronization message, which is simultaneously transmitted to the other three components, from which each internal computer of a component determines a correction term for the tick counter contained in its component and corrects the reading of the local tick counter by this correction term.
Timing synchronization over cable networks
In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.
Multihost clock synchronization
In one embodiment, a network interface card device includes communication interfaces to provide data connection with respective local devices configured to run respective clock synchronization clients, at least one network interface to provide data connection between a packet data network and ones of the local devices, and a hardware clock to maintain a time value, and serve the clock synchronization clients.
Device and method for providing a clock signal to an application
Embodiments of the present invention relate to a method and a device for providing a clock signal to an application, comprising (a) determining a time difference between a clock device and the clock signal; if the time difference is above a predetermined threshold x, (b) calibrating a first time unit and, during calibrating the first time unit, (c) using a second time unit for providing the clock signal to the application.
Fault-tolerant distribution unit and method for providing fault-tolerant global time
The invention relates to a method for providing a fault-tolerant global time and for the fault-tolerant transport of time-controlled messages in a distributed real-time computer system which comprises external computers and a fault-tolerant message distribution unit, FTMDU. The FTMDU comprises at least four components which supply the global time to the external computers by means of periodic external synchronization messages, wherein the external computers each set their local clock to the received global time, wherein each external sender of a time-controlled message transmits two message copies of the message to be sent via two different communication channels to two different components of the FTMDU at periodic sending times defined a priori in timetables, wherein these two message copies are delivered within the FTMDU via two independent communication paths to those two components of the FTMDU which are connected to an external receiver of the message via communication channels.
Software-controlled clock synchronization of network devices
A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.
SYNCHRONIZING UPDATE OF TIME OF DAY COUNTERS USING TIME STAMP EXCHANGE OVER A CONTROL PLANE
A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.
APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
NETWORK SWITCH AND CIRCUIT BOARD WHERE PRECISION TIME PROTOCOL MODULE IS USED
A network switch can include a precision time protocol (PTP) module and a circuit board. The PTP module can provide a first clock signal and include a predetermined interface. The circuit board can include a socket, an oscillator and a selection unit. The socket can be inserted by the predetermined interface to receive the first clock signal. The oscillator can provide a second clock signal. The selection unit can include a first terminal, a second terminal, an output terminal and a selection terminal. The first terminal can receive the first clock signal when the predetermined interface is inserted into the socket. The second terminal can receive the second clock signal. The output terminal can output one of the first clock signal and the second clock signal. The selection terminal can receive a selection signal to control the output terminal to output the first clock signal or the second clock signal.