An optical transmission device includes: a receiver configured to receive a signal including data; a generator configured to generate an output clock to output the data based on a signal clock synchronized with the signal; and a controller configured to control a frequency of the output clock based on a first amount of the data so that the output clock follows a clock of a transmission source of the data.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

A cross connect apparatus or system with transparent clocking, consistent with embodiments described herein, connects a selected source or ingress port to a selected destination or egress port and clocks data out of the selected egress port using a synthesized clock that is adjusted to match a recovered clock from the selected ingress port. A transparent clocking system may generate the synthesized clock signal with adjustments in response to a parts per million (PPM) rate detected for the associated recovered clock signal provided by the selected ingress port. The cross connect system with transparent clocking may be a 400 G cross connect system with 10 G resolution. The cross connect system with transparent clocking may be used in optical transport network (OTN) applications, for example, to provide an aggregator and/or an add-drop multiplexer (ADM) or to provide a reconfigurable optical add-drop multiplexer (ROADM) upgrade to a higher data rate.

A signal processing method executed by a transmission device, the signal processing method includes receiving a plurality of frame signals; extracting a plurality of synchronization signals each for performing frame synchronization and separating data of each of the plurality of frame signals, from the received plurality of frame signals; storing the data of each of the plurality of frame signals in a memory intermittently, using respective pulse widths of the plurality of synchronization signals as intervals, based on timing at which the plurality of synchronization signals are extracted; detecting timing at which data at a predetermined location in the frame signal is written to the memory, from the timing at which the plurality of synchronization signals are extracted; and reading data of each of the plurality of frame signals from the memory according to the detected timing.

A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.

A transmission apparatus includes: a first mapping unit configured to allocate a first frame that stores a client signal to an intermediate frame; a second mapping unit configured to allocate the intermediate frame to a second frame that has a higher bit rate than a bit rate of the first frame; and a rate controller configured to control a bit rate of the intermediate frame based on the bit rate of the first frame and the bit rate of the second frame.

Systems and methods are described, and one method includes allocate a continuous duration within a TDMA scheme, for asynchronous NOMA transmissions, and extending from an allocation start time to an allocation termination time, formed of contiguous time slots of the TDMA scheme, and included providing to asynchronous NOMA user terminals an indication of the allocation start time and termination time, indicating allowance to perform asynchronous NOMA transmissions within a start time constraint that starts of the asynchronous NOMA transmissions do not precede the allocation start time, and terminations of the asynchronous NOMA transmissions do not succeed the allocation termination time.

In various embodiments, a method is provided. In this method, a first signal is received from a master node, and is sampled to obtain a first sample. The first sample is then quantized to obtain a quantized form of the first sample. A first synchronization sequence is detected from the quantized form of the first sample at T2. First information is received from the master node and the first information is used to indicate a moment T1 at which the master node sends the first synchronization sequence. A second synchronization sequence is sent to the master node at T3. Second information received from the master node and the second information is used to indicate a moment T4 at which the master node detects a quantized form of the second synchronization sequence. Time synchronization is performed based on T1, T2, T3, and T4.

This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.