Techniques for computing electrical phase of electrical metering devices are described. In an example, data indicating zero-crossing times at first and second metering devices is obtained. A time-difference between the zero-crossing times may be determined. In a first example, the time-difference may be based at least in part on calculations involving a first value of a first free-run timer on a first metering device, a second value of a second free-run timer on a second metering device, and a time of a transmission between the metering devices. In a second example, the time-difference may be based at least in part on calculations involving a start or end time of a time-slot of a spread spectrum radio frequency transmission scheme. A phase difference between the first zero-crossing and the second zero-crossing may be determined, based at least in part on the determined time-difference.

Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.

An embodiment generates a composite high speed clock with embedded frame synchronization using simple digital encoding of a high speed reference clock. The high speed reference clock and self-aligned frame synchronization signal are recovered by standard logic gate circuitry. The encoding and decoding circuits are comprised of basic digital logic gates with low propagation delay skew and timing jitter. The encoded clock is easier to transmit from source unit to destination unit over common transmission media (i.e., digital transceivers, amplifiers, splitters, connectors and coaxial cable) because only a single interface is required and because the encoding scheme reduces the composite clock to a minimal transmission bandwidth with constrained waveform harmonic content, relative to a low frequency frame sync with fast rise time that requires a broadband transmission media.

Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.

Systems and methods are disclosed for detection of a selected signal pattern, such as a servo sector preamble, and for frequency offset determination. A circuit may be configured to divide a signal into detection windows of a selected size, and sample the signal a selected number of times within each detection window. The circuit may then determine an error value for each detection window based on values of the samples for each detection window, and determine the preamble is detected when a threshold number of most-recently sampled detection windows have error values below a threshold value. The circuit may then organize the sample values corresponding to the preamble into groups, and calculate phase estimates representing a phase at which the groups were sampled. The circuit may determine a frequency offset based on the phase estimates, and modulate the sampling frequency according to the frequency offset.

A baseband filter unit inputs a received signal including a sine wave at least in a portion of the received signal. A differentiator differentiates the received signal. A first correlator correlates the received signal differentiated and a cosine waveform. An acquisition unit acquires a value of the received signal as an offset value, at a time estimated based on a result of correlation in the first correlator and at a time when the received signal includes a sine waveform. A correction unit corrects the received signal in accordance with the offset value acquired in the acquisition unit.

A receiver configuration for a control unit in a vehicle having a voltage generator for generating a synchronization pulse, which includes a first voltage source, a current source and a current sink, the voltage generator generating the synchronization pulse within predefined specification limits having a predefined shape and a predefined time behavior, and the receiver configuration outputting the synchronization pulse for synchronizing a signal transmission via a databus to at least one sensor. A method is also provided for generating a synchronization pulse. The voltage generator generates the synchronization pulse via the current source and the current sink by charging and/or discharging a bus load essentially as a sinusoidal oscillation.

In a method for operating a device comprising an internal clock generator and an internal clock and being connected to a network, the internal clock is incremented by the internal clock generator. Moreover, the internal clock is synchronized with a network frequency of the network.

A baseband filter unit inputs a received signal including a sine wave at least in a portion of the received signal. A differentiator differentiates the received signal. A first correlator correlates the received signal differentiated and a cosine waveform. An acquisition unit acquires a value of the received signal as an offset value, at a time estimated based on a result of correlation in the first correlator and at a time when the received signal includes a sine waveform. A correction unit corrects the received signal in accordance with the offset value acquired in the acquisition unit.

A synchronization pattern detector is disclosed. The synchronization pattern detector includes a plurality of cost function engines which each calculate a partial cost of a subset of the incoming data bits. The cost function engines are arranged in a two dimensional array where each row processes data samples associated with a particular phase of the incoming data bits. These partial costs are summed together to calculate a total cost for a particular symbol stream. Summing circuits are configured to calculate costs for various scenarios, such as transmit baudrate equal to the receiver baudrate; transmit baudrate slower than the receiver baudrate; and transmit baudrate faster than the receiver baudrate. In addition to detecting the synchronization pattern, the detector may also provide information that is used to adjust parameters of the read circuit to better align the receiver baudrate to the transmit baudrate.