A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

The invention relates to a method for transmitting an actuation signal and a first data signal between a control device and an actuation device of a power semiconductor device. To minimize the expenditure for the operation of the physical transmission channels and the costs for the laying of the physical connection between control device and actuation device, the transmission of the actuation signal and the first data signal between the control device and the actuation device takes place simultaneously and via a common transmission channel, wherein the first data signal is combined with the actuation signal by means of a digital modulation method or coding method. A feedback signal and second data signal are transmitted in the opposite direction. A first coding length is shorter than the interval length of the actuation signal. A second coding length is shorter than the interval length: of the feedback signal.

An electronic controller of a restraint control system for a vehicle comprises an electronic control unit including a first serial interface. The electronic controller also comprises a communications controller including a second serial interface and a plurality of PSI5 (Peripheral Sensor Interface 5) digital communications interfaces. Each of the first and second serial interfaces are Serial Peripheral Interfaces (SPI) in direct communications with one another, and the digital communications interfaces are each configured to communicate with a remote sensor. The communications controller is configured to transmit a voltage sync pulse to each of the remote sensors via the PSI5 digital communications interfaces in response to a synchronization command received from the electronic control unit via the serial interconnection. The voltage sync pulses on each of the PSI5 interfaces may be staggered and non-overlapping to reduce EMI production and to reduce the current load of the electronic controller.

A communication device includes a sampler configured to sample an input signal, wherein the sampler is configured to generate a sampled value for each sampling time of a sequence of sampling times, a sequence value generator configured to generate an output value for each sampling time of the sequence of sampling times based on the sampled values, wherein the sequence value generator is configured to set the output value for a sampling time based on the sampled value for the sampling time and based on a limitation of the difference between the output value for the sampling time and the output value for the preceding sampling time in the sequence of sampling times, and an edge detector configured to detect an edge in the input signal based on the output values.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

A circuit system includes: a receiver circuit which outputs a periodic voltage pulse via a bus line; and an ascertaining device configured to ascertain whether the voltage on the bus line has reached a specified threshold value. The circuit system is configured to start the reception of data signals a specified time period after an instant at which the voltage on the bus line has reached the specified threshold value.

An input/output (I/O) and control system for long distance communications and industrial applications having a bus and protocol for communications between field devices and a channel generator for monitoring and control of the field devices. The channel generator produces an offset square wave of configurable frequency on the bus, and sends a synchronization pulse of selected duration at the start of each bus scan cycle in a pulse train cycle to reset counters in the field devices before the bus scan cycle is repeated, to ensure field devices are synchronized, transmitters transmit on the correct channel, and receivers sample the pulse cycle at the correct time. Changing the synchronization pulse length increases bandwidth for shorter, less noisy and more stable systems and inversely decreases bandwidth for increased noise immunity and distance for longer, noisier and less stable systems.

An electronic controller of a restraint control system for a vehicle comprises an electronic control unit including a first serial interface. The electronic controller also comprises a communications controller including a second serial interface and a plurality of PSI5 (Peripheral Sensor Interface 5) digital communications interfaces. Each of the first and second serial interfaces are Serial Peripheral Interfaces (SPI) in direct communications with one another, and the digital communications interfaces are each configured to communicate with a remote sensor. The communications controller is configured to transmit a voltage sync pulse to each of the remote sensors via the PSI5 digital communications interfaces in response to a synchronization command received from the electronic control unit via the serial interconnection. The voltage sync pulses on each of the PSI5 interfaces may be staggered and non-overlapping to reduce EMI production and to reduce the current load of the electronic controller.

The purpose of the present invention is to cause a reception side communication device to appropriately detect a start bit. A serial communication unit (100), which transmits serial data by a combination of a high level signal and a low level signal, is provided with: a serial communication part (111) that provides the start bit on the head of the serial data, and transmits the high level signal in a prescribed duration just before the start bit; and a duration setting part (113) that sets the duration.

Systems, methods, and apparatuses are discussed that enable robust, high-speed communication of sensor data. One example system includes a sensor bus, an electronic control unit (ECU), and one or more sensors. The ECU is coupleable to the sensor bus and configured to generate a synchronization signal, and is configured to output the synchronization signal to the sensor bus. The one or more sensors are also coupleable to the sensor bus, and at least one sensor of the one or more sensors is configured to sample sensor data in response to the synchronization signal and to output the sampled sensor data to the sensor bus.