A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

A printed circuit board according to an embodiment includes: an insulating layer including a via hole; and a via disposed in the via hole of the insulating layer, wherein the via includes; a connection portion disposed in the via hole of the insulating layer; a first pad disposed on an upper surface of the insulating layer and an upper surface of the connection portion; and a second pad disposed under a lower surface of the insulating layer and a lower surface of the connection portion, wherein the upper surface of the connection portion has a concave shape in a downward direction, the lower surface of the connection portion has a concave shape in an upward direction, a lower surface of the first pad has a convex shape corresponding to the upper surface of the connection portion, and an upper surface of the second pad has a convex shape corresponding to the lower surface of the connection portion.

A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via portion disposed in the first insulating layer; and a second via portion disposed in the second insulating layer; wherein the first via portion includes: a first via part passing through the first insulating layer; a first-first pad disposed on an upper surface of the first insulating layer and connected to an upper surface of the first via part; and a first-second pad disposed on a lower surface of the first insulating layer and connected to a lower surface of the first via part; wherein the second via portion includes: a second via part passing through the second insulating layer and having a lower surface connected to an upper surface of the first-first pad; a second pad disposed on an upper surface of the second insulating layer and connected to an upper surface of the second via part; wherein a width of the first-first pad is smaller than or equal to a width of the upper surface of the first via part; and wherein a width of the second pad is smaller than or equal to a width of the upper surface of the second via part.

Embodiments disclosed herein comprise package substrates and methods of forming package substrates. In an embodiment, a package substrate comprises a core substrate. A hole is disposed into the core substrate, and a via is disposed in the hole. In an embodiment, the via completely fills the hole. In an embodiment, a method of forming a package substrate comprises exposing a region of a core substrate with a laser. In an embodiment, the laser changes the morphology of the exposed region. The method may further comprise etching the core substrate, where the exposed region etches at a faster rate than the remainder of the core substrate to form a hole in the core substrate. The method may further comprise disposing a via in the hole.

A wiring circuit board includes a porous insulating layer, and a first conductive layer sequentially toward one side in the thickness direction. The first conductive layer includes a first signal wire and first ground wires. Each of the first ground wires is thicker than the first signal wire.

A wiring substrate includes an insulating layer including resin and filler particles, conductor layers including an upper-layer conductor layer and a lower-layer conductor layer such that the insulating layer is sandwiched between the upper-layer and lower-layer conductor layers, and a penetrating conductor formed in the insulating layer such that the penetrating conductor is penetrating through the insulating layer and connecting the upper-layer and lower-layer conductor layers. The penetrating conductor is formed such that the penetrating conductor has a first length which is the maximum width of the penetrating conductor in the direction orthogonal to the thickness direction of the wiring substrate and the first length is 25 μm or less, and the insulating layer is formed such that the maximum particle size of the filler particles in a region within the distance of 40% of the first length from the penetrating conductor is 20% or less of the first length.

An electronic-component carrier board includes carrier plates formed in a stack, and insulating layers each disposed between two adjacent ones of the carrier plates. Multiple conductive pins extend through the insulating layers and the carrier plates. Multiple conductive wires equal in length and width are provided. Each conductive wire is connected to one of the conductive pins, covered by one of the insulating layers, disposed between two adjacent ones of the carrier plates, and extends outwardly from the stack of the carrier plates. A wiring method for the electronic-component carrier board is also disclosed.

For example, an apparatus may include a Printed Circuit Board (PCB) including a Ball Grid Array (BGA) on a first side of the PCB, the BGA configured to connect a Surface Mounted Device (SMD) to the PCB; an antenna disposed on a second side of the PCB opposite to the first side, the antenna to communicate a Radio Frequency (RF) signal of the SMD; and an RF transition to transit the RF signal between the BGA and the antenna, the RF transition including a plurality of signal buried-vias; a first plurality of microvias configured to transit the RF signal between the plurality of signal buried-vias and a ball of the BGA, the first plurality of microvias are rotationally misaligned with respect to the plurality of signal buried-vias; and a second plurality of microvias configured to transit the RF signal between the plurality of signal buried-vias and the antenna.

A multilayer substrate includes a base body including a first main surface, a first external electrode provided on the first main surface and made of metal foil, a first interlayer connection conductor, and a second interlayer connection conductor having higher conductivity than the first interlayer connection conductor. The base body includes insulating base material layers that are stacked on one another. The first interlayer connection conductor is provided at least in an insulating base material layer on which the first external electrode is provided, and is connected to the first external electrode. The second interlayer connection conductor is disposed inside the base body, and is connected to the first external electrode through the first interlayer connection conductor.

An example electronic device includes a housing, a first board and a second board disposed in an interior of the housing and disposed to face each other in a first direction, an interposer extending to surround an interior space between the first board and the second board, a first conductive layer disposed to face the first board and including a first conductive area, a second conductive layer disposed to face the second board and including a second conductive area, an insulation layer disposed between the first conductive layer and the second conductive layer, a first insulation part disposed between the first conductive layer and the first board and covering the first conductive area, a second insulation part disposed between the second conductive layer and the second board and covering the second conductive area, a first plating area extending from the first conductive layer to the second conductive layer, on a first side surface of the insulation layer, and a second plating area extending from the first conductive layer to the second conductive layer, on a second side surface of the insulation layer.