Implementations described and claimed herein provide thin film devices and methods of manufacturing and implanting the same. In one implementation, a shaped insulator is formed having an inner surface, an outer surface, and a profile shaped according to a selected dielectric use. A layer of conductive traces is fabricated on the inner surface of the shaped insulator using biocompatible metallization. An insulating layer is applied over the layer of conductive traces. An electrode array and a connection array are fabricated on the outer surface of the shaped insulator and/or the insulating layer, and the electrode array and the connection array are in electrical communication with the layer of conductive traces to form a flexible circuit. The implantable thin film device is formed from the flexible circuit according to the selected dialectic use.

The present invention provides a conductive fabric comprising base cloth and a conductive metallic circuit structure formed on the surface of the base cloth. The conductive metallic circuit structure comprises at least one metallic seed layer and at least one chemical-plating layer. The metallic seed layer is an evaporation-deposition layer or a sputter-deposition layer and has a circuit pattern. The chemical-plating layer is applied over the surface of the metallic seed layer. The conductive fabric has improved conductivity and heat generation efficiency.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity, medium-photosensitivity, and low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

A circuit layer is formed by drilling vias and forming channels in a circuit layer which has catalytic particles exposed on the surfaces, channels, and vias. A first flash electroless deposition is followed by application of dry film, followed by selective laser ablation of the dry film channels and vias. A second electroless solution is applied which provides additional deposition over the first flash electroless deposition but only on the vias and trace channel areas. An electrodeposition follows, using the first deposition as a cathode. The dry film is stripped and the first electroless layer is etched, leaving only depositions in the channels and vias.

A method for forming a circuit board having a dielectric core, a foil top surface, and a thin foil bottom surface with a removable foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling utilizes a sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step, which provide dot vias of fine linewidth and resolution.

A circuit board according to an embodiment includes an insulating layer; a first circuit pattern disposed on a first surface of the insulating layer; a first solder resist disposed on the first surface of the insulating layer; and a first barrier layer including a first-first portion disposed between the first solder resist and the first circuit pattern, and a first-second portion disposed between the insulating layer and the first circuit pattern; wherein the firs-first portion of the first barrier layer includes: a first-first gold (Au) layer disposed under a lower surface of the first circuit pattern; and a first-first palladium (Pd) layer disposed under a lower surface of the first-first gold (Au) layer; wherein the first-second portion of the first barrier layer includes: a first-second gold (Au) layer disposed to surround a side surface and an upper surface of the first circuit pattern; and a first-second palladium (Pd) layer disposed to surround the first-second gold (Au) layer; and wherein the first circuit pattern is not in contact with the first solder resist and the insulating layer by the first-first portion and the first-second portion of the first barrier layer.

A novel method for the manufacturing of fine line circuitry on a transparent substrates is provided, the method comprises the following steps in the given order providing a transparent substrate, depositing a pattern of light-shielding activation layer on at least a portion of the front side of said substrate, placing a photosensitive composition on the front side of the substrate and on the pattern of light-shielding activation layer, photo-curing the photosensitive composition from the back side of the substrate with a source of electromagnetic radiation, removing any uncured remnants of the photosensitive composition; and thereby exposing recessed structures and deposition of at least one metal into the thus formed recessed structures whereby a transparent substrate with fine line circuitry thereon is formed. The method allows for very uniform and fine line circuitry with a line and space dimension of 0.5 to 10 μm.

A resilient electrical connector assembly includes a base PCB and stacked layers of interconnected resilient conductive structures where each structure has at least two resilient conductive strips and at least two conductive contacts. One contact is integrated with a conductive path on the base PCB and another contact pad is positioned to establish a conductive path with a target PCB when the latter is mounted parallel to the base PCB. The resilient conductive strips flex due to a compressive force exerted between the base PCB and target PCB on the stacked layers. The resilient conductive structures are formed by depositing metal to sequentially form each of the stacked layers with one contact being initially formed in engagement with the conductive path on the base PCB.