Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.

A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple first active pillars above the substrate, a memory structure, multiple transistors, and multiple second active pillars. The multiple first active pillars are arranged in an array along a first direction and a second direction. The substrate includes an isolation structure on which the first active pillars are located. The memory structure includes first electrode layers, a dielectric layer and a second electrode layer. The first electrode layer covers a sidewall of the first active pillar, the dielectric layer covers at least surfaces of the first electrode layers, the second electrode layer covers a surface of the dielectric layer. Each of the second active pillars is located above a corresponding one of the first active pillars; a channel structure of each transistor is located in the second active pillar.

A semiconductor structure includes a substrate, and a plurality of first semiconductor columns, a storage structure, a plurality of transistors and a first protective layer located above the substrate. The plurality of first semiconductor columns are arranged in array in first and second directions. Each first semiconductor column includes a first part and a second part located on same. The second part includes a bottom portion, an intermediate portion and a top portion. The first direction and the second direction intersect with each other and are both parallel to top surface of the substrate. The storage structure surrounds sidewalls of the first parts. The first protective layer surrounds sidewalls of the top portions of the second parts. A channel structure of each transistor is located in the intermediate portion of the second part, and an extending direction of the channel structure is the same as that of the second part.

A semiconductor structure, a method for manufacturing a semiconductor structure, and a memory are provided. The semiconductor structure includes: a plurality of first semiconductor pillars, a plurality of second semiconductor pillars, a first support layer, and a storage structure. The plurality of first semiconductor pillars are arranged in an array in a first direction and in a second direction. Each of the first direction and the second direction is perpendicular to an extending direction of each first semiconductor pillar, and the first direction intersects with the second direction. The first support layer covers sidewalls of top portions of the plurality of first semiconductor pillars. Each second semiconductor pillar is arranged on a respective one of the plurality of first semiconductor pillars. The storage structure is arranged around at least sidewalls of the plurality of first semiconductor pillars and sidewalls of the plurality of second semiconductor pillars.

A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array on the substrate, where the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially, and along a second direction, a cross-sectional area of the second segment is smaller than those of the first segment and the third segment; forming a gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a gate dielectric layer on the gate oxide layer, where the gate dielectric layer is shorter than the gate oxide layer, and is close to the third segment.

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an array region, where the array region is provided with a plurality of active pillars; a plurality of bit lines extending along a first direction, where the bit line is located at a bottom of the active pillar; and a plurality of word lines extending along a second direction, where any one of the word lines covers sidewalls of a column of the active pillars arranged along the second direction; and the first direction and the second direction form a predetermined angle, and the predetermined angle is an acute angle or an obtuse angle.