According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

An array substrate, a display panel and a display device are disclosed. The array substrate includes a first data line and a second data line which extend substantially along a first direction and are adjacent to each other, a first gate line and a second gate line that extend substantially along a second direction intersected with the first direction and are adjacent to each other, and at least two sub-pixels which are sequentially arranged in parallel along the first direction; the first gate line and the second gate line are disposed at two sides of the at least two sub-pixels in the first direction, respectively.

An array substrate, a display panel and a display device are disclosed. The array substrate includes a first data line and a second data line which extend substantially along a first direction and are adjacent to each other, a first gate line and a second gate line that extend substantially along a second direction intersected with the first direction and are adjacent to each other, and at least two sub-pixels which are sequentially arranged in parallel along the first direction; the first gate line and the second gate line are disposed at two sides of the at least two sub-pixels in the first direction, respectively.

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (ROM) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (ROM) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.

A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.

A semiconductor device includes a latch including a first-node and a second-node. A first-transistor is between the first-node and a first-BL and has a gate connected to a WL. A second-transistor is between the second-node and a second-BL and has a gate connected to the WL. A power-supply line is connected to the latch. A third-transistor is connected between the first-node and a reference-voltage source. A fourth-transistor is between the second-node and the reference-voltage source and has a gate connected to the reference-voltage source. A signal line is connected to a gate of the third-transistor. In a first-mode, the power-supply line supplies a first-voltage to the latch and the signal line brings the third-transistor to a non-conduction state. In a second-mode, the power-supply line supplies a second-voltage to the latch and the signal line brings the third-transistor to a conduction state and connects the first-node to the reference-voltage source.

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (ROM) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.