A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second group of word lines formed on the active region, and the second group of word lines includes at least two word lines. The ROM device structure further includes an isolation line between the first group of word lines and the second group of word lines and over the active region. The first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer.

The present invention discloses a mixed three-dimensional memory (3D-M.sub.x). Both data and codes are stored in a same 3D-M.sub.x die. Data, which require a lower cost per bit and can tolerate slow access, are stored in large memory arrays, whereas codes, which require fast access and can tolerate a higher cost per bit, are stored in small memory arrays.

The present description concerns a ROM including at least one first rewritable memory cell.

An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

A memory cell is disclosed. In an embodiment a programmable read-only memory cell includes a first insulating layer located between a semiconductor body and a second conductive or semi-conductive layer, wherein the first insulating layer comprises a peripheral portion and a central portion, and wherein the peripheral portion has a greater thickness than the central portion.

The present description concerns a ROM including at least one first rewritable memory cell.

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first high-voltage junction formed in the substrate, and a second high-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first high-voltage junction and the second high-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third high-voltage junction formed in the substrate, and a fourth high-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third high-voltage junction and the fourth high-voltage junction.

An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first high-voltage junction formed in the substrate, and a second high-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first high-voltage junction and the second high-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third high-voltage junction formed in the substrate, and a fourth high-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third high-voltage junction and the fourth high-voltage junction.

A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell.