A nitride semiconductor light emitting element includes: an n-side semiconductor layer; a p-side semiconductor layer; and an active layer positioned between the n-side semiconductor layer and the p-side semiconductor layer. The active layer includes, successively from a n-side semiconductor layer side: a first barrier layer containing Al and an n-type impurity, a first well layer containing Al and emitting ultraviolet light, a second barrier layer containing Al, and a second well layer containing Al and emitting ultraviolet light. A highest n-type impurity concentration peak in the first barrier layer is located in a portion of the first barrier layer that is closer to the p-side semiconductor layer than to the n-side semiconductor layer. An Al composition ratio of the first barrier layer is higher than an Al composition ratio of the second barrier layer.

A chip structure is provided. The chip structure includes: a chip wafer unit and a color conversion layer unit arranged on a light-exit side of the chip wafer unit. The chip wafer unit includes a plurality of sub-pixel light-emitting function layers. The color conversion layer unit includes color conversion layers arranged on the light-exit side of the chip wafer unit. The chip structure further includes: an attaching layer, arranged between the chip wafer unit and the color conversion layer unit and configured to attach the chip wafer unit and the color conversion layer unit.

Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. The bonding material contains nickel (Ni). The method also includes placing the light emitting structure onto a silicon substrate with the bonding material in contact with the silicon substrate and annealing the light emitting structure and the silicon substrate. As a result, a nickel silicide (NiSi) material is formed at an interface between the silicon substrate and the bonding material to mechanically couple the light emitting structure to the silicon substrate.

In an embodiment an optoelectronic semiconductor component includes a first semiconductor layer of an n-conductivity type, the first semiconductor layer being of Al.sub.xGa.sub.1-xN composition, with 0.3x0.95, a second semiconductor layer of a p-conductivity type, an active zone between the first semiconductor layer and the second semiconductor layer, the active zone including a quantum well structure and an intermediate layer between the first semiconductor layer and the active zone, wherein the intermediate layer includes a semiconductor material of Al.sub.yGa.sub.1-yN composition, with x*1.05y1, and wherein the intermediate layer is located directly adjacent to the active zone.

A polychrome wafer structure (100,200,200) comprising a plurality of structured first epitaxial dies (102) having first light-emitting devices (107) configured to emit light of a first color, at least a plurality f structured second epitaxial dies (103) having second light-emitting devices (107) configured to emit light of a second color. The plurality of the structured first epitaxial dies (102) and the plurality of the structured second epitaxial dies (103) are bonded on a target wafer (507) with a plurality of common monolithic integrated circuits in a manner that the at least one first die and the at least one second die is connected to common monolithic integrated (101) one circuit for simultaneously driving at least one first epitxial die (102) having light-emitting device (107) and at least one second epitaxial die (103) having light-emitting device (107) by the respective one common monolithic integrated circuit (101).

A process for manufacturing an electroluminescent device, comprising: (a) using a stack comprising, successively: a substrate having a surface; matrix arrays of pixels formed on the surface of the substrate, of columnar shape; an encapsulating layer arranged to cover the matrix arrays of pixels; a dielectric layer formed on the encapsulating layer; (b) performing a directional etch along the normal to the surface of the substrate, of a portion of the dielectric layer extending between the pixels of the matrix arrays of pixels; the dielectric layer having a portion remaining at the end of step (b); and (c) performing a selective chemical etch of the remaining portion of the dielectric layer with a chemical etchant that permits selective etching of the remaining portion of the dielectric layer with respect to the encapsulating layer.

A light emitting diode epitaxial structure (LEDES) based on an aluminum gallium nitride material and a manufacturing method thereof are described. The LEDES includes a first layer of n-type aluminum gallium nitride, an active layer comprising aluminum gallium nitride, a p-type aluminum gallium nitride, and a second layer of n-type aluminum gallium nitride disposed above the p-type aluminum gallium nitride along an epitaxial growth direction. An epitaxial layer comprising a gallium nitride layer is contained between an epitaxial layer of the p-type aluminum gallium nitride and an epitaxial layer of the second layer of n-type aluminum gallium nitride. The epitaxial layer comprising the gallium nitride layer has an energy band width smaller than those of the epitaxial layers of the p-type aluminum gallium nitride and the second layer of n-type aluminum gallium nitride. A coarsened structure exists on a surface of the second layer of n-type aluminum gallium nitride.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

A light-emitting diode manufacturing method including the forming of three-dimensional semiconductor elements, extending along parallel axes, made of a III-V compound, each having a lower portion and a flared upper portion inscribed within a frustum of half apical angle . The method further comprises, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor layer of the III-V compound covering the active area by vapor deposition at a pressure lower than 10 mPa, by using a flux of the group-III element along a direction inclined by an angle III and a flux of the group-V element along a direction inclined by an angle V with respect to the vertical axis, angles III and V being smaller than angle .

A semiconductor device includes a channel layer including a first group III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer including a second group III-V semiconductor material that is different than the first group III-V semiconductor material; a plurality of sources/drains spaced apart from each other on an upper surface of the barrier layer; a gate insulating layer covering the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains; a gate provided on an upper surface of the gate insulating layer, the gate not overlapping the plurality of sources/drains; a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and a gate electrode electrically connected to the gate, wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement.