A coated conductor comprises a substrate supporting a ReBCO superconductor adapted to carry current in a superconducting state. The superconductor is characterized in having peaks in critical current (J.sub.c) of at least 0.2 MA/cm.sup.2 in a magnetic field of about 1 Tesla when the field is applied normal to the surface of the superconductor and when the field is applied parallel to the surface of the superconductor, and further characterized in that the superconductor includes horizontal defects and columnar detects in a size and an amount sufficient to result in the said critical current response. The conductor is characterized in that the ratio of the height of the peaks in the J.sub.c is in the range from 3:1 with the ratio of the field perpendicular (0 degrees) to the field parallel (+/−90 degrees) to the range from 3:1 with the ratio of the field parallel to the field perpendicular.

According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.

Techniques for trapping quasiparticles in superconductor devices are provided. A superconductor device can comprise a substrate layer. The superconductor device can further comprise a first superconductor layer composed of a first superconductor material, on a first surface of a substrate layer. The superconductor device can further comprise a trapping material buried in the first superconductor layer, wherein the trapping material is formulated to trap quasiparticles.

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

A method and a system for fabricating superconducting nanowire single photon detector (SNSPD) is disclosed. The superconducting nanowire single photon detector consists of a thin film of superconducting material shaped into a meandering nanowire through nanofabrication processes. The pattern enables the nanowire to cover a wide surface area. The SNSPD is a type of near-infrared single-photon detector based on a current-biased superconducting nanowire. The method includes depositing a plurality of buffer layers on a substrate of a superconducting nanowire single photon detector using a pulsed laser deposition technique. The method further includes designing deposited buffer layer into a desired pattern of nanostrips and depositing a plurality of high temperature superconductor (HTS) on the desired pattern of nanostrips. To obtain the desired pattern, at least one of lithography and/or etching processes is used in the SNSPD.

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

A method of fabricating a superconducting wire includes forming a buffer layer on the substrate, the buffer layer including an Al.sub.2O.sub.3 layer, the Al.sub.2O.sub.3 layer being formed by reactive magnetron sputtering in which first oxygen gas as reactant gas and a sputtering target made of aluminium metal are used, the Al.sub.2O.sub.3 layer being formed while being supplied the first oxygen gas at a first concentration, the first concentration being a concentration of the first oxygen gas at which an emission intensity of Al in plasma near a surface of the sputtering target is not less than 25% and not more than 80% of a first reference value, the first reference value being the emission intensity of Al at which the concentration of the first oxygen gas is zero; and forming a superconducting layer above the buffer layer.

A method for fabricating a second generation high-temperature superconductor (2G-HTS) tape, including: (S1) depositing a superconducting thin film on a surface of a ductile metal substrate with a buffer layer; (S2) forming a micro-holes array pattern on a surface of the superconducting thin film by etching using a reel-to-reel dynamic femtosecond infrared laser etching system, where the micro-holes array pattern covers the superconducting thin film; (S3) depositing a superconducting thick film on the surface of the superconducting thin film; and (S4) depositing a silver protective layer and a copper stabilization layer on a surface of the superconducting thick film.

An oxide superconducting wire, includes a laminate including a base material, an intermediate layer, and an oxide superconducting layer, the intermediate layer being laminated on a main surface of the base material, the intermediate layer being constituted of one or more layers having an orientation, the intermediate layer having one or more first non-orientation regions extending in a longitudinal direction of the base material, the oxide superconducting layer being laminated on the intermediate layer, the oxide superconducting layer having a crystal orientation controlled by the intermediate layer, the oxide superconducting layer having second non-orientation regions located on the first non-orientation regions, and a metal layer which covers at least a front surface and side surfaces of the oxide superconducting layer in the laminate.

The present invention relates to a precursor (1) for production of a high-temperature superconductor (HTS) in ribbon form, comprising a metallic substrate (10) in ribbon form having a first ribbon side (11) and a second ribbon side (12), wherein, on the first ribbon side (11), (a) the substrate (10) has a defined texture as template for crystallographically aligned growth of a buffer layer or an HTS layer and (b) an exposed surface of the substrate (10) is present or one or more layers (20,30) are present that are selected from the group consisting of: buffer precursor layer, pyrolyzed buffer precursor layer, buffer layer, HTS precursor layer, pyrolyzed HTS buffer precursor layer and pyrolyzed and further consolidated HTS buffer precursor layer, and, on the second ribbon side (12), at least one ceramic barrier layer (40) that protects the substrate (10) against oxidation or a precursor which is converted to such a layer during the HTS crystallization annealing or the pyrolysis is present, wherein, when one or more layers (20, 30) are present on the first ribbon side (11), the ceramic barrier layer (40) or the precursor thereof has a different chemical composition and/or a different texture than the layer (20) arranged on the first ribbon side (11) and directly adjoining the substrate (10). In this precursor, the barrier layer (40) is a layer that delays or prevents ingress of oxygen to the second ribbon side (12) and is composed of conductive ceramic material or a precursor which is converted to such a precursor during the HTS crystallization annealing or the pyrolysis, and the ceramic material is an electrically conductive metal oxide or an electrically conductive mixture of metal oxides, wherein the conductive metal oxide or one or more metal oxides in the conductive mixture is/are preferably metal oxide(s) doped with an extraneous metal.