Silicon carbide semiconductor element and fabrication method thereof

Abstract

In a fabrication method of a silicon carbide semiconductor element including a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, dicing is added to form at least one dicing line in an element active region on a surface of the semiconductor substrate on a side opposite of the drift layer before forming the ohmic electrode on the backside of the semiconductor substrate. Thus, a silicon carbide semiconductor element and fabrication method thereof is provided such that even if the semiconductor substrate is made thinner to reduce the on-resistance, the strength of the substrate can be maintained and cracking of the wafer during wafer processing can be reduced.

Claims

1. A fabrication method of a silicon carbide semiconductor element that includes a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, the fabrication method comprising: forming one or more slit-shaped grooves in an element active region on a surface of the semiconductor substrate on a side opposite of the drift layer before forming the ohmic electrode on the backside of the semiconductor substrate; the one or more slit-shaped grooves are formed by a dicing blade; and the dicing blade is applied directly to a furthest most edge of a first end of the semiconductor substrate and across a certain direction of the semiconductor substrate which is perpendicular to a surface of the substrate contacting the drift layer, and the dicing blade is separated from the semiconductor substrate before reaching a second end of the semiconductor substrate on a side opposite to an incident direction of the dicing blade so as to maintain an un-diced substrate peripheral portion; and a distance between the one or more slit-shaped grooves is made smaller than a thickness of the dicing blade such that an entire surface directly underlying the backside of the semiconductor element is made thinner leaving the un-diced substrate peripheral portion.

2. The fabrication method of a silicon carbide semiconductor element according to claim 1, wherein processes of reactive ion etching (RIE) and sacrificial oxidation are added for removing damage occurring with the forming of the one or more slit-shaped grooves.

3. A silicon carbide semiconductor element including a drift layer playing a role of retaining a high withstand voltage on a front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on a backside, wherein the semiconductor substrate has a substrate resistance reduced by providing one or more slit-shaped grooves in an element active region on a surface on a side opposite of the drift layer, and the one or more slit-shaped grooves are provided from a furthest most peripheral end of the semiconductor substrate in a direction which is perpendicular to the surface of the semiconductor substrate contacting the drift layer, and are formed with a substrate end remaining at least on a side opposite of the furthest most peripheral end of the semiconductor substrate so as to maintain an un-diced substrate peripheral portion; and a distance between the one or more slit-shaped grooves is made smaller than a thickness of dicing such that an entire surface directly underlying the backside of the semiconductor element is made thinner leaving the un-diced substrate peripheral portion.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic cross-sectional view of an example of a structure of a Schottky barrier diode (SBD) using silicon carbide for a substrate;

(2) FIG. 2 is a schematic cross-sectional view of a cross section of a portion of a diced substrate;

(3) FIG. 3 is a plane view of an example of dicing lines that are cutting traces of dicing;

(4) FIG. 4 is an explanatory view of making a dicing pitch (W.sub.P) smaller than a dicing blade width (W.sub.B) so that an entire surface of a SiC substrate 1 can be ground with an end portion of the SiC substrate 1 left;

(5) FIG. 5 is a schematic cross-sectional view of an element, depicting an appearance of a Schottky barrier diode completed by the method of the present invention;

(6) FIG. 6 is a characteristic diagram of forward IV characteristics without dicing and with a dicing pitch of 100 μm and a dicing depth of 300 μm;

(7) FIG. 7 is a characteristics diagram of substrate resistance in a case of performing dicing in stripes by using dicing pitch and dicing depth as parameters;

(8) FIG. 8 is a characteristics diagram of a forward voltage reduction value at 400 A/cm.sup.2 in a case of performing dicing in stripes by using dicing pitch and dicing depth as parameters;

(9) FIG. 9 is a characteristics diagram of substrate resistance in a case of performing dicing in a lattice by using dicing pitch and dicing depth as parameters;

(10) FIG. 10 is a characteristic diagram of the forward voltage reduction value at 400 A/cm.sup.2 in a case of performing dicing in a lattice by using dicing pitch and dicing depth as parameters;

(11) FIG. 11 is a characteristics diagram of dicing depth dependency of substrate resistance when the dicing pitch is made smaller than the dicing blade width; and

(12) FIG. 12 is a characteristics diagram of the reduction value of forward voltage drop at 400 A/cm.sup.2 when the dicing pitch is made smaller than the dicing blade width.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

(13) A method of the present invention is characterized in having a step of dicing such that at least one dicing line is formed on a back surface of a semiconductor substrate before forming an ohmic electrode on the backside of the semiconductor substrate in a fabrication method of a silicon carbide semiconductor element having a drift layer playing a role of retaining a high withstand voltage on the front side of a semiconductor substrate of silicon carbide and having an ohmic electrode on the backside.

(14) First, description will be made of an example of the fabrication method of a silicon carbide semiconductor element including a drift layer playing a role as a withstand voltage region retaining a high withstand voltage on the front side of a semiconductor substrate of silicon carbide and including an ohmic electrode on the backside with reference to FIG. 1 described above.

(15) A 4H—SiC substrate (hereinafter referred to as the SiC substrate) 1 is prepared and an n-type epitaxial layer 2 acting as the drift layer is grown thereon. The concentration of impurities such as nitrogen atoms added as n-type impurities in this case and the thickness of the later to be grown differ depending on the withstand voltage class and, in the case of an element of a 600 to 1200 V class, in general, the concentration of impurities is set to a first half of 1×10.sup.16 cm.sup.−3 level and the layer thickness is set to 5 to 10 μm. In a surface layer of the n-type epitaxial layer 2 in an element active region on the SiC substrate 1 with the n-type epitaxial layer 2 grown thereon, a JBS structure 3 is selectively formed by Al ion implantation. The JBS structure 3 is for reducing leak current during the opposite direction. For the purpose of improving the element withstand voltage, Al ion implantation is performed into peripheral edge portion 4 of the active region such that a dose amount of 10.sup.12 to 10.sup.13 cm.sup.−2 is achieved. Al of the ion implantation is annealed and electrically activated at a temperature around 1600 degrees C. The front surface of the SiC substrate 1 is coated with the thermal oxide film (a deposition oxide film, the field oxide film) 5. The ohmic electrode (ohmic alloy layer) 6 is formed on the back surface of the SiC substrate 1, and the Schottky electrode 7 and the Al electrode 8 for bonding with an Al wire are sequentially formed on the front surface of the SiC substrate 1. The lamination metal 9 for increasing adhesiveness with solder is subsequently formed on the back surface of the SiC substrate 1, and a preprocessing step for fabricating the silicon carbide semiconductor element depicted in FIG. 1 is terminated.

(16) In the present invention, before the step of forming the ohmic electrode 6 on the backside of the SiC substrate 1 described above, i.e., after completion of the steps of growing the n-type epitaxial layer 2 acting as the drift layer on the SiC substrate 1, forming the JBS structure 3 and the peripheral edge portion 4 of the active region through the ion implantation of the p-type impurities, annealing for activation, and forming the field oxide film 5, the back surface of the SiC substrate 1 is diced by a dicing saw. The dicing in this case is performed by using a dicing blade such as a diamond blade, for example.

(17) In the present invention, the back surface of the SiC substrate 1 is diced to form at least one dicing line under an element active region. FIG. 2 is a schematic cross-sectional view of a cross section of a portion of a diced substrate. In FIG. 2, W.sub.B, D.sub.B, W.sub.P, and t.sub.SUB denote a width of a dicing blade, a height (depth) of dicing, a dicing pitch, and a thickness of the SiC substrate 1, respectively. Although W.sub.B, D.sub.B, and W.sub.P can be determined arbitrarily in the present invention, the dicing blade width (W.sub.B) is normally 60 μm, preferably 120 μm. When the dicing depth (D.sub.B) is deeper, the substrate resistance can further be reduced; however, the dicing depth must be kept within a range not reaching the drift layer formed on the front side of the SiC substrate 1, i.e., within a range of the thickness (t.sub.SUB) of the SiC substrate 1. When the dicing pitch (W.sub.P) is smaller, the substrate resistance can further be reduced. Although the dicing pitch (W.sub.P) can be made smaller than the dicing blade width (W.sub.B) to grind the entire surface of the SiC substrate 1 for thinning, if the entire surface of the SiC substrate 1 is ground, an end portion of the SiC substrate 1 is preferably left uncut so as to maintain the mechanical strength as described later.

(18) Although the direction and the shape of dicing are not particularly limited in the present invention, for example, the dicing may be formed in stripes in one direction of the SiC substrate 1 or may be formed in two orthogonal directions on the SiC substrate 1, i.e., in a lattice. FIG. 3 is a plane view of an example of dicing lines that are cutting traces of dicing. In the present invention, as depicted in FIG. 3, the dicing lines can be formed from one end of the SiC substrate 1 in a certain direction so as not to reach the other end on the opposite side such that an end portion of the SiC substrate 1 is left uncut, thereby further improving the mechanical strength of the SiC substrate 1.

(19) FIG. 4 is an explanatory view of making the dicing pitch (W.sub.P) smaller than the dicing blade width (W.sub.B) so that the entire surface of the SiC substrate 1 can be ground with an end portion of the SiC substrate 1 left. A method depicted in FIG. 4 is achieved by further developing the method depicted in FIG. 3 and the dicing is performed in one direction such that an end portion of the SiC substrate 1 remains as is the case with the method depicted FIG. 3; however, in a cross section along a section line A-A′, as depicted in FIG. 2, the dicing pitch (W.sub.P) is made smaller than the dicing blade width (W.sub.B) so that the entire surface of the SiC substrate 1 can be ground.

(20) FIG. 5 is a schematic cross-sectional view of an element, depicting an appearance of a Schottky barrier diode completed by the method of the present invention. FIG. 5 depicts an appearance of the Schottky barrier diode completed by sequentially performing a step of forming the ohmic electrode (ohmic metal) 6, a step of forming a contact hole for Schottky metal, a step of forming the Schottky electrode (Schottky metal) 7, a step of forming the Al electrode (top Al metal) 8, and a step of forming the lamination metal (back-surface three-layer metal) 9 after forming at least one dicing line under the element active region on the backside of the SiC substrate 1 in the method as depicted in FIG. 3 or 4.

(21) In the present invention, after dicing, processes of reactive ion etching (RIE) and sacrificial oxidation are preferably added for removing damage of the dicing. The sacrificial oxidation is to thermally oxidize the SiC substrate 1 and immediately remove a thermal oxide film formed by the thermal oxidization with dilute hydrofluoric acid, etc. for removing a surface layer formed by the step of RIE and this thermal oxide film is temporarily formed for making the surface of the SiC substrate 1 clean and is called a sacrificial oxide film.

(22) Although the fabrication method is described by taking an SBD as an example, the method of the present invention is applicable to any vertically-structured power devices such as MOSFETs, IGBTs, SBDs, and pin diodes.

Embodiment

(23) Detailed description will hereinafter be made by taking the simply-structured Schottky barrier diode used in the description of the conventional technique as an example with reference to FIG. 1.

(24) On the 4H—SiC substrate 1 having a diameter of 4 inches with a thickness of 350 μm and specific resistance of 20 mΩcm, the steps were performed as the step of growing the n-type epitaxial layer 2 acting as the drift layer, the step of forming the JBS structure 3 and the peripheral edge portion 4 of the active region through the ion implantation of the p-type impurities, the step of annealing for activation, and the step of forming the field oxide film 5, as described above. In this example, the nitrogen atom concentration at the ion implantation was 1×10.sup.16 cm.sup.−3, and the film thickness of the n-type epitaxial layer 2 was 10 μm. The back surface of the SiC substrate 1 was subsequently diced by a dicing saw. In this case, the dicing was performed by using a dicing blade such as a diamond blade. The width (W.sub.B) of the dicing blade used in this example was 60 μm. The height (D.sub.B) of the dicing and the dicing pitch (W.sub.P) in this case were used as parameters to conduct experiments.

(25) The dicing height (D.sub.B) and the dicing pitch (W.sub.P) were changed from 50 μm to 250 μm and from 100 μm to 1 mm, respectively. Two types of dicing directions were used for conducting the experiments in one direction and in two orthogonal directions. In the case of dicing in one direction, the dicing was performed from a certain direction and the dicing blade was pulled up to leave a cutting margin of 10 mm from the wafer outer circumferential end in the end portion on the opposite side (see FIG. 3).

(26) The reactive ion etching using mixed gas of CF.sub.4 and O.sub.2 was then performed for removing a damage layer due to the dicing. The etching depth was 1 μm. The process of sacrificial oxidation was performed by two-hour dry oxidization at a temperature of 1100 degrees and, after the formation of a thermal oxide film of about 100 nm, the thermal oxide film was removed by dipping into buffered hydrofluoric acid solution.

(27) Subsequently, the Schottky barrier diode was completed by sequentially performing the formation of the ohmic electrode 6, the formation of the contact hole for Schottky metal, the formation of the Schottky electrode 7, the formation of the Al electrode 8, and the formation of the lamination metal 9 as described in the conventional technique (see FIG. 5). The dicing step and the damage removal step of the back surface may be inserted into any step before forming the ohmic electrode 6.

(28) In the forward IV characteristics of the SBD produced in this way, while a rising voltage is unchanged, a slope becomes steeper. FIG. 6 is a characteristic diagram of the forward IV characteristics without dicing and with a dicing pitch of 100 μm and a dicing depth of 300 μm. At a current density of 400 A/cm.sup.2, a reduction in forward voltage by 0.14 V was realized. In FIG. 6, reference numeral 11 denotes the presence of the back surface dicing and reference number 12 denotes the absence of the back surface dicing.

(29) With reference to FIGS. 7 to 10, description will be made of forward voltage reduction values at 400 A/cm.sup.2 in the cases of performing the dicing in stripes and performing the dicing in two orthogonal directions (in a lattice) by using the dicing pitch and the dicing depth as parameters. FIG. 7 is a characteristics diagram of substrate resistance in the case of performing the dicing in stripes by using the dicing pitch and the dicing depth as parameters. FIG. 8 is a characteristics diagram of the forward voltage reduction value at 400 A/cm.sup.2 in the case of performing the dicing in stripes by using the dicing pitch and the dicing depth as parameters. FIG. 9 is a characteristics diagram of substrate resistance in the case of performing the dicing in a lattice by using the dicing pitch and the dicing depth as parameters. FIG. 10 is a characteristic diagram of the forward voltage reduction value at 400 A/cm.sup.2 in the case of performing the dicing in a lattice by using the dicing pitch and the dicing depth as parameters.

(30) FIGS. 7 and 8 depict the substrate resistance and the forward voltage reduction value at 400 A/cm.sup.2, respectively, in the case of performing the dicing in stripes, and FIGS. 9 and 10 depict the substrate resistance and the forward voltage reduction value at 400 A/cm.sup.2, respectively, in the case of performing the dicing in a lattice. As can be seen from FIGS. 7 to 10, when the dicing pitch is smaller or when the dicing depth is larger, the substrate resistance is further reduced. It is found that the substrate resistance is further reduced when stripes are defined in two directions rather than one direction.

(31) FIG. 11 is a characteristics diagram of dicing depth dependency of substrate resistance when the dicing pitch is made smaller than the dicing blade width. FIG. 12 is a characteristics diagram of the reduction value of forward voltage drop at 400 A/cm.sup.2 when the dicing pitch is made smaller than the dicing blade width. As can be seen from FIGS. 11 and 12, when the dicing depth is deeper, the substrate resistance is further reduced, and the substrate resistance is 0.1 mΩcm.sup.2 at the depth of 300 μm. Therefore, a larger amount of grinding of a substrate results in further reduction in substrate resistance.

INDUSTRIAL APPLICABILITY

(32) As described above, a silicon carbide semiconductor element and a fabrication method thereof according to the present invention are useful for a vertical power semiconductor device used for a power semiconductor element.

EXPLANATIONS OF LETTERS OR NUMERALS

(33) 1 SiC substrate 2 n-type epitaxial layer 3 junction barrier Schottky (JBS) structure 4 peripheral edge portion 5 thermal oxide film (deposition oxide film) 6 ohmic electrode 7 Schottky electrode 8 Al electrode for bonding with an Al wire 9 lamination metal D.sub.B dicing depth W.sub.B dicing blade width W.sub.P dicing pitch t.sub.SUB substrate thickness