Power semiconductor

Abstract

A power semiconductor is provided. The power semiconductor includes a gate, a source, a silicon chip and a drain. The source includes a first copper particle layer and a first metal layer. The first copper particle layer covers the upper surface of the first metal layer. The silicon chip is bonded to the lower surface of the first metal layer. The drain is bonded to the lower surface of the silicon chip. The thickness of the first copper particle layer is greater than the thickness of the first metal layer. All copper mentioned are of large grain copper with size greater than 0.25 um.

Claims

1. A power semiconductor comprises: a gate; a source comprising: a first copper particle layer as thickness in 5 μm˜100 μm, the first copper particle layer formed by plating and stacking a plurality of large-grain copper; and a first metal layer covering the bottom surface of the first copper particle layer; a silicon chip bonded to the lower surface of the first metal layer; and a drain bonded to the lower surface of the silicon chip; wherein, the thickness of the first copper particle layer is greater than the thickness of the first metal layer.

2. The power semiconductor of claim 1, wherein the first copper particle layer is as size in 2 μm˜50 μm.

3. The power semiconductor of claim 1, wherein the first metal layer is made of aluminum, and the thickness of the first metal layer is 0.25 μm˜6 μm or 0.25 μm˜1 μm.

4. The power semiconductor of claim 1, wherein the gate comprises a fourth copper particle layer and a fourth metal layer, and the fourth copper particle layer covers the top surface of the fourth metal layer, and the thickness of the fourth copper particle layer is 5 μm˜100 μm.

5. A power semiconductor comprises: a gate; an emitter comprising: a first copper particle layer as thickness in 5 μm˜100 μm, the first copper particle layer formed by plating and stacking a plurality of large-grain copper; and a first metal layer covering the bottom surface of the first copper particle layer; a silicon chip bonded to the lower surface of the first metal layer; and a collector bonded to the lower surface of the silicon chip; wherein, the thickness of the first copper particle layer is greater than the thickness of the first metal layer.

6. The power semiconductor of claim 5, wherein the first copper particle layer is as size in 2 μm˜50 μm.

7. The power semiconductor of claim 5, wherein the first metal layer is made of aluminum, and the thickness of the first metal layer is 0.25 μm˜6 μm or 0.25 μm˜1 μm.

8. The power semiconductor of claim 5, wherein the gate comprises a fourth copper particle layer and a fourth metal layer, and the fourth copper particle layer covers the top surface of the fourth metal layer and the thickness of the fourth copper particle layer is 5 μm˜100 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a perspective of the power semiconductor 10 of prior art.

(2) FIG. 2 shows a perspective of power semiconductor 20 of first embodiment.

(3) FIG. 3 shows comparison chart of resistance with first copper particle layers 24C of different thicknesses and 6 μm aluminum pad.

(4) FIG. 4 shows perspective of the power semiconductor 30 of second embodiment.

(5) FIG. 5 shows perspective of the power semiconductor 40 of third embodiment.

(6) FIG. 6 shows perspective of different exterior of the power semiconductor 40.

(7) FIG. 7 shows perspective of the power semiconductor 40 of fourth embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(8) With reference to FIG. 2 for a perspective of power semiconductor 20 of first embodiment. The power semiconductor 20 includes a source bonding end 24E, a source 24, a gate 22, a silicon chip 25, a drain 26, a drain bonding end 26E, and a metal frame 27. The gate 22 is disposed between the source 24 and the drain 26. The source 24 includes a first copper particle layer 24C and a first metal layer 24T. The first copper particle layer 24C is bonded to the source bonding end 24E via a metal wire 24L, and it covers on the top surface of the first metal layer 24T, which is made by aluminum with thickness of 0.25 μm˜1 μm. The thickness of the first copper particle layer 24C is thicker than the first metal layer 24T.

(9) In addition, the first copper particle layer 24C is formed by plating stacking a plurality of large-grain copper or a plurality of stacking tiny copper particles, and the large-grain copper as size in 2 μm˜50 μm would be better option in this embodiment. In practical application, the thickness of the first copper particle layer 24C is generally 5 μm˜100 μm so that thicker first copper particle layer 24C can effectively reduce resistance and improve cooling of the power semiconductor 20.

(10) In addition, the silicon chip 25 is bonded to the below surface of the first metal layer 24T; the drain 26 is boned to the below surface of the silicon chip 25; the metal frame 27 is disposed below the drain 26; the drain bonding end 26E is bonded to the metal frame 27.

(11) In the above, costs of sputtering and dry etch can be significantly reduced while increasing productivity in processing of the power semiconductor 20 when the thickness of first metal layer 24 is reduced from 6 um to 0.25 μm˜1 μm. Furthermore, although aluminum of thickness in the range of 0.25 μm˜1 μm has high resistance, the thick first copper particle layer 24C has significantly lower resistance so that the electrons would choose the first copper particle layer 24C as the main conductor. The first copper particle layer 24C can prevent metal atoms from being affected by heat and large currents when the power semiconductor 20 need to be able to withstand high currents and not to produce high temperatures. Electro migration caused by affected atoms can form voids between the first copper particle layer 24C and the first metal layer 24T, subsequently affect electron flow, and causes the power semiconductor 20 to be damaged. This is a very common reliability failure problem for power transistors and the applying of a thick large grain copper layer can effectively eliminate this problem.

(12) With reference to FIG. 3, a comparison chart for resistance of first copper particle layers 24C of different thicknesses to the resistance of 6 μm aluminum pad. Applicant used a plurality of first copper particle layers 24C of different thicknesses to measure resistance of electron flows laterally spreading in the first copper particle layers 24C and the traditional 6 μm aluminum pad structure. Applicant further compared resistance of the first copper particle layers 24C with 6 μm aluminum pad structure, and the final results are shown as in the comparison chart of FIG. 3. The FIG. 3 clearly shows resistance of the first copper particle layers 24C is 0.340 when the thickness of the first copper particle layers 24C is 5 μm, and the ratio to resistance of the traditional 6 μm aluminum pad structure of 0.5330 is 64%, a 36% reduction! In addition, resistance of the first copper particle layers 24C becomes lower when the thickness of the first copper particle layers 24C is thicker. For example, the resistance of the first copper particle layer 24C when its thickness is increased to 10 μm dropped to 0.17Ω, and its ratio to the 6 μm aluminum pad structure becomes only 32%. Furthermore, the resistance of the first copper particle layer 24C when its thickness is further increased to 50 μm dropped to only 0.034Ω, and its ratio to the 6 μm aluminum pad structure is a mere 6%. The resistance of the first copper particle layer 24C when its thickness goes all the way up to 100 μm dropped to 0.017Ω, and its ratio to the 6 μm aluminum pad structure becomes 3%. Therefore, it is clear that when the first copper particle layer 24C has a thickness of 5 μm or more, it can significantly improve performance and reliability of the power semiconductor 20 when compared to those using 6 μm aluminum pad structure for the source 14. Furthermore, if the thickness of the first copper particle layer 24C is equal to or thicker than 5 μm, the cooling efficiency would also be significantly improved so that it helps to boost the overall reliability life performance of the power semiconductor 20.

(13) In addition, it can also be concluded with FIG. 3, the flattened resistance of 0.017Ω of first copper particle layer 24C with thickness of 100 μm, 105 μm or 110 μm, the ratio of resistivity to the 6 μm aluminum pad structure becomes a constant 3%. Therefore, the decreasing of resistance of the first copper particle layer 24C slows down and enters a plateau when the thickness of the first copper particle layer 24C becomes thicker than 100 μm. The performance improvement of the power semiconductor 20 is therefore, limited and stopped beyond this point.

(14) In summary, FIG. 3 shows that the first copper particle layer 24C with thickness of 5 μm˜100 μm can greatly improve performance and reliability of the power semiconductor 20. However, large-grain copper must be used to avoid electro migration from happening. Voids will still happen to affect reliability if tiny grain copper is used.

(15) With reference to FIG. 4 for perspective of the power semiconductor 30 of second embodiment. The difference between power semiconductor 30 and power semiconductor 20 is that original source 24 is replaced with emitter 34, and the drain 26 is replaced with collector 36 in the power semiconductor 30. The emitter 34 similarly includes a first copper particle layer 34C and a first metal layer 34T, which is equivalent to first copper particle layer 24C. In addition, the source bonded end 24E is replaced with emitter bonded end 34E; the drain bonded end 26E is replaced with collector bonded end 36E. In detail, the power semiconductor 30 is an IGBT-type power semiconductor. Electron would choose the first copper particle layer 34C as conductor because which has lower resistance. The use of the first copper particle layer 34C can avoid voids formation by electro migration with the first metal layer 34T and cause damage to the power semiconductor 30. This is only possible when large grain copper is used for the first copper particle layer 34C.

(16) With reference to FIG. 5 for perspective of the power semiconductor 40 of third embodiment. The power semiconductor 40 includes a gate 42, a source 44, a plurality of first long-strip metal source layer 440, a drain 46 and a plurality of second long-strip metal drain layer 460. The source 44 includes a first copper particle layer 44C and a first metal layer 44T, which as thickness in 0.25 μm˜6 μm (preferably 0.25 μm˜6 μm) is aluminum. In addition, the first copper particle layer 44C is covered on the top surface of the first metal layer 44T, and the thickness of the first copper particle layer 44C is thicker than the first metal layer 44T.

(17) The drain 46 includes a second copper particle layer 46C and a second metal layer 46T, which as thickness in 0.25 μm˜6 μm (preferably 0.25 μm˜1 μm) is aluminum and covered on the top surface of the second metal layer 46T, and the thickness of the second copper particle layer 46C is thicker than the second metal layer 46T.

(18) Every first long-strip metal source layer 440 is bonded to the source 44 via a tiny first metal pillar 441. In detail, every first long-strip metal source layer 440 can be considered as extended structure of the source 44 because the first long-strip metal source layer 440 is bonded to the first metal layer 44T of the source 44.

(19) Every second long-strip drain metal layer 460 is bonded to the drain 46 via a tiny second metal pillar 461. In detail, every second long-strip drain metal layer 460 can be considered as extended structure of the drain 46 because second long-strip drain metal layer 460 is bonded to the drain 46.

(20) In practical application, the thickness of first copper particle layer 44C and second copper particle layer 46C are generally 5 μm˜100 μm so that thicker first copper particle layer 44C and second copper particle layer 46C can effectively improve transverse conductivity and cooling of the power semiconductor 40. In above, the gate 42 includes a plurality of branch structure 420, which is disposed between the first long-strip source metal layer 440 and the second long-strip drain metal layer 460 to form the transistor structure.

(21) Next, the working principle of the power semiconductor 40 is explained as follows:

(22) The electron current from source 44 would enter the first long-strip source metal layer 440 from top to bottom via the first metal pillar 441 after the gate 42 enables electron flow by turning on the transistor, and then electron moves to the second long-strip drain metal layer 460. Finally, the electrons move upward to the drain 46 via the second metal pillar 461. The gate opens the channel between source 440 and drain 460 to make electron flow from source to drain, it is a typical working scheme for transistor. The first copper particle layer 44C and the second copper particle layer 46C similarly can improve lateral electron flow and prevent damage to the power semiconductor 40 when the power semiconductor 40 need to withstand high current flow and maximize heat dissipation.

(23) In the power semiconductor 40, a third copper particle layer (not be drawn) is disposed on the top surface of the first long-strip metal layer 440 and the second first long layer 460. The structure of the third copper particle layer is stacked by large-grain copper as the first copper particle layer 44C and second copper particle layer 46, and the thickness of the third copper particle layer is 5 μm˜100 μm. Therefore, the third copper particle layer can effectively improve electron flow on the first long-strip metal layer 440 and the second long-strip metal layer 460 and reduce operating temperature of the power semiconductor 40.

(24) With reference to FIG. 6 for perspective of different exterior of the power semiconductor 40. The exterior of the power semiconductor 40 can be presented as FIG. 6 besides FIG. 5, it can reduce moving obstacle of electron and increase cooling speed. The difference between the power semiconductor 40 in FIG. 6 and FIG. 5 is that the branch structure 420, the first long-strip metal layer 440 and the second long-strip metal layer 460 of the power semiconductor 40 can all be formed by the same metal layer in FIG. 5, but in FIG. 6, the branch structure 420 of the power semiconductor 40 passed through below the second long-strip metal layer 460 so that they need be formed separately by doped silicon instead of formed by the same metal layer.

(25) With reference to FIG. 7 for perspective of the power semiconductor 40 of fourth embodiment. The difference between the power semiconductor 40 of FIG. 6 and FIG. 5 is that gate 52 of the power semiconductor 50 includes a fourth copper particle layer 52C and a fourth metal layer 52T. The fourth copper particle layer 52C is covered on the top surface of the fourth metal layer 52T, and the thickness of the fourth metal layer 52T is 5 μm˜100 μm so that the fourth copper particle layer 52C can improve electron flow in the gate 52 and reduce operating temperature of the power semiconductor 50.

(26) In addition, the power semiconductor of the instant application also can be used to BCD Technology. In detail, one BCD chip can include Bipolar, CMOS and DMOS, which is a power device as shown in FIG. 5 and FIG. 6 with the instant application. All copper mentioned are of large grain copper with size greater than 0.25 um.

(27) In summary, the power semiconductor of the instant application can reduce electron movement obstruction inside, improve cooling speed itself and has much better performance and reliability. While the preferred embodiment of the invention have been set forth for the purpose of disclosure, modifications of the disclosed embodiments of the invention as well as other embodiments thereof may occur to those skilled in the art. Accordingly, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the invention.