Fabrication method of semiconductor package with stacked semiconductor chips

Abstract

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

Claims

1. A fabrication method of a semiconductor package, comprising the steps of: providing a carrier having a first surface with a plurality of conductive pads and a second surface opposite to the first surface; disposing a first semiconductor chip on the first surface of the carrier in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively; thinning the first semiconductor chip from the first non-active surface thereof; forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof; forming in the first through holes a plurality of bumps electrically connected to the first electrode pads, and forming a heat conducting layer on the first non-active surface of the first semiconductor chip, wherein a solder material is formed on and in direct contact with the bumps; disposing an electronic element on the first semiconductor chip and electrically connecting the electronic element and the bumps; and forming on the first surface of the carrier an encapsulant that encapsulates the first semiconductor chip and the electronic element.

2. The fabrication method of claim 1, wherein the first electrode pads are exposed through the first through holes, respectively.

3. The fabrication method of claim 1, wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.

4. The fabrication method of claim 1, wherein the bumps are formed through an electroplating process or an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) process, or formed through solder paste print and reflow.

5. The fabrication method of claim 1, wherein the electronic element is a semiconductor chip, a passive component or a semiconductor package.

6. The fabrication method of claim 1, wherein the carrier is a circuit board or a packaging substrate.

7. The fabrication method of claim 1, wherein the encapsulant further comprises a first body encapsulating the first semiconductor chip and a second body encapsulating the electronic element.

8. The fabrication method of claim 1, further comprising disposing a second semiconductor chip between the first semiconductor chip and the electronic element.

9. The fabrication method of claim 1, further comprising forming on the first non-active surface of the first semiconductor chip a circuit layer electrically connected to the bumps.

10. The fabrication method of claim 1, further comprising attaching a heat sink to the encapsulant.

11. The fabrication method of claim 10, further comprising forming a thermal adhesive between the heat sink and the encapsulant.

12. The fabrication method of claim 1, further comprising attaching a heat sink to the encapsulant and connecting the heat sink to the heat conducting layer.

13. A fabrication method of a semiconductor package, comprising the steps of: providing a carrier having a first surface with a plurality of conductive elements and a second surface opposite to the first surface; disposing a first semiconductor chip on the first surface of the carrier in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive elements, respectively; thinning the first semiconductor chip from the first non-active surface thereof; forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof; forming in the first through holes a plurality of first bumps made of solder electrically connected to the first electrode pads; disposing an electronic element on the first semiconductor chip and electrically connecting the electronic element to the first bumps; and forming on the first surface of the carrier an encapsulant that encapsulates the first semiconductor chip and the electronic element.

14. The fabrication method of claim 13, wherein the first electrode pads are exposed through the first through holes, respectively.

15. The fabrication method of claim 13, wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.

16. The fabrication method of claim 13, wherein the first bumps are formed through an electroplating process or an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) process, or formed through solder paste print and reflow.

17. The fabrication method of claim 13, wherein the electronic element is a semiconductor chip, a passive component or a semiconductor package.

18. The fabrication method of claim 13, wherein the carrier is a silicon wafer, an aluminum coated wafer or a glass sheet.

19. The fabrication method of claim 13, wherein the encapsulant further comprises a first body encapsulating the first semiconductor chip and a second body encapsulating the electronic element.

20. The fabrication method of claim 13, further comprising disposing a second semiconductor chip between the first semiconductor chip and the electronic element.

21. The fabrication method of claim 13, further comprising forming on the first non-active surface of the first semiconductor chip a circuit layer electrically connected to the first bumps.

22. The fabrication method of claim 13, further comprising attaching a heat sink to the encapsulant.

23. The fabrication method of claim 22, further comprising forming a thermal adhesive between the heat sink and the encapsulant.

24. The fabrication method of claim 13, further comprising forming a heat conducting layer on the first non-active surface of the first semiconductor chip.

25. A fabrication method of a semiconductor package, comprising the steps of: providing a carrier having opposite first and second surfaces, wherein a build-up structure is formed on the first surface of the carrier and has a plurality of conductive pads exposed from a top surface thereof; disposing a first semiconductor chip on the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively, and a plurality of first bumps made of solder are formed in the first semiconductor chip and electrically connected to the first electrode pads; thinning the first semiconductor chip from the first non-active surface thereof so as to expose the first bumps; disposing an electronic element on the first semiconductor chip and electrically connecting the electronic element and the first bumps; and forming on the build-up structure an encapsulant that encapsulates the first semiconductor chip and the electronic element.

26. The fabrication method of claim 25, wherein the build-up structure has a plurality of bonding pads in contact with the first surface of the carrier, and the method further comprises removing the carrier to expose the bonding pads.

27. The fabrication method of claim 25, wherein the electronic element is a semiconductor chip, a passive component or a semiconductor package.

28. The fabrication method of claim 25, wherein the carrier is a silicon wafer, an aluminum coated wafer or a glass sheet.

29. The fabrication method of claim 25, wherein each of the conductive pads further comprises a first solder material or an ENEPIG layer formed thereon.

30. The fabrication method of claim 25, wherein the encapsulant further comprises a first body encapsulating the first semiconductor chip and a second body encapsulating the electronic element.

31. The fabrication method of claim 25, further comprising disposing a second semiconductor chip between the first semiconductor chip and the electronic element.

32. The fabrication method of claim 25, further comprising forming on the first non-active surface of the first semiconductor chip a circuit layer electrically connected to the first bumps.

33. The fabrication method of claim 25, further comprising attaching a heat sink to the encapsulant.

34. The fabrication method of claim 33, further comprising forming a thermal adhesive between the heat sink and the encapsulant.

35. The fabrication method of claim 25, further comprising forming a heat conducting layer on the first non-active surface of the first semiconductor chip.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIGS. 1-1 to 1-33 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a first embodiment of the present invention, wherein FIGS. 1-7′ and 1-8′ show another embodiment of FIGS. 1-7 to 1-12, FIGS. 1-12′ to 1-17′ show another embodiment of FIGS. 1-12 to 1-17, FIGS. 1-21′ and 1-22′ show another embodiment of FIGS. 1-21 to 1-25, and FIG. 1-32′ shows another embodiment of FIG. 1-32;

(2) FIGS. 2-1 to 2-3 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a second embodiment of the present invention;

(3) FIGS. 3-1 to 3-10 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a third embodiment of the present invention;

(4) FIG. 4 is a schematic cross-sectional view showing a semiconductor package according to a fourth embodiment of the present invention, wherein FIG. 4′ shows another embodiment of FIG. 4;

(5) FIGS. 5-1 to 5-5 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a fifth embodiment of the present invention;

(6) FIGS. 6-1 to 6-6 are schematic cross-views showing a semiconductor package and a fabrication method thereof according to a sixth embodiment of the present invention, wherein FIG. 6-6′ shows another embodiment of FIG. 6-6; and

(7) FIGS. 7-1 to 7-5 and FIGS. 8-1 to 8-3 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a seventh embodiment of the present invention, wherein FIGS. 8-1 to 8-3 show another embodiment of FIGS. 7-4 and 7-5.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(8) The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

(9) It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms such as “top”, “bottom”, “on”, “one” etc. are merely for illustrative purpose and should not be construed to limit the scope of the present invention.

First Embodiment

(10) FIGS. 1-1 to 1-33 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a first embodiment of the present invention.

(11) Referring to FIG. 1-1, a carrier 10 having a first surface 10a and a second surface 10b opposite to the first surface 10a is provided. A first dielectric layer 11a is formed on the first surface 10a and a plurality of openings 110a are formed in the first dielectric layer 11a for exposing a portion of the first surface 10a. The carrier 10 can be, but not limited to, a silicon wafer, an aluminum coated wafer or a glass sheet. If the surfaces of the carrier 10 such as an aluminum-coated wafer are conductive, an electrical test can be performed to determine the yield of circuits on the carrier 10. The first dielectric layer 11a can be made of benzocylcobuthene (BCB), polyimide, polybenzoxazole (PBO), SiO.sub.2 or Si.sub.3N.sub.4.

(12) Referring to FIG. 1-2, a first conductive layer 12a is formed on the first surface 10a and the first dielectric layer 11a by sputtering.

(13) Referring to FIG. 1-3, a first resist layer 13 is formed on the first conductive layer 12a and a plurality of openings 130 are formed in the first resist layer 13 for exposing a portion of the first conductive layer 12a.

(14) Referring to FIG. 1-4, a first circuit layer 12b is formed on the exposed portion of the first conductive layer 12a. The first circuit layer 12b can be made of copper or aluminum.

(15) Referring to FIG. 1-5, the first resist layer 13 and the portion of the first conductive layer 12a covered by the first resist layer 13 are removed such that the first dielectric layer 11a, and the remaining portion of the first conductive layer 12a and the first circuit layer 12b form a build-up structure. It should be noted that the build-up structure is not limited to the drawing.

(16) Referring to FIG. 1-6, a second dielectric layer 11b is formed on the first dielectric layer 11a and the first circuit layer 12b, and a plurality of openings 110b are formed in the second dielectric layer 11b such that a portion of the first circuit layer 12b is exposed through the openings 110b to serve as conductive pads 131. The second dielectric layer 11b can be made of benzocylcobuthene (BCB), polyimide, polybenzoxazole (PBO), SiO.sub.2 or Si.sub.3N.sub.4.

(17) Referring to FIG. 1-7, a second conductive layer 14 is formed on the second dielectric layer 11b and the first circuit layer 12b by sputtering.

(18) Referring to FIG. 1-8, a second resist layer 15 is formed on the second conductive layer 14 and a plurality of openings 150 are formed in the second resist layer 15 for exposing a portion of the second conductive layer 14.

(19) Referring to FIG. 1-9, a first solder material 16 such as Sn—Ag is formed on the exposed portion of the second conductive layer 14.

(20) Referring to FIG. 1-10, the second resist layer 15 and the portion of the second conductive layer 14 covered by the second resist layer 15 are removed.

(21) Referring to FIG. 1-11, the first solder material 16 is reflowed.

(22) Referring to FIG. 1-12, an electronic element such as a first semiconductor chip 17 is provided. The first semiconductor chip 17 has a first active surface 17a and a first non-active surface 17b opposite to the first active surface 17a. The first active surface 17a has a plurality of first electrode pads 171. A copper pillar 172 and a third solder material 173 are sequentially formed on each of the first electrode pads 171. Alternatively, referring to FIG. 1-12′, only a third solder material 173 is formed on each of the first electrode pads 171 and no copper pillar 172 is formed between the third solder material 173 and the first electrode pad 171.

(23) It should be noted that the steps of FIGS. 1-7 to 1-12 can be simplified as an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) process or the like so as to facilitate subsequent solder bonding with the semiconductor chip. For example, referring to FIGS. 1-7′ and 1-8′, an ENEPIG layer 161 can be formed in the openings 110b of the second dielectric layer so as to dispense with the reflow process of FIG. 1-11. Further, the conductive pads 131 can be electrically connected to the first electrode pads 171 of the first semiconductor chip 17 through the ENEPIG layer 161. Alternatively, the step of FIG. 1-9 can be replaced with an ENEPIG process or the like so as to increase solder bonding area with the semiconductor chip and dispensed with the reflow process of FIG. 1-11. This can be readily understood by those skilled in the art upon reading the present disclosure and thus is not described further herein.

(24) Referring to FIG. 1-13, the first semiconductor chip 17 is disposed on the first solder material 16 in a flip-chip manner and a first underfill 18a is formed between the first semiconductor chip 17 and the second dielectric layer 11b.

(25) Referring to FIG. 1-14, a first encapsulant 19a is formed on the second dielectric layer 11b for encapsulating the first semiconductor chip 17 and the first underfill 18a.

(26) Referring to FIG. 1-15, a grinding process is performed to remove a portion of the first encapsulant 19a from the first non-active surface 17b of the first semiconductor chip 17 and thin the first semiconductor chip 17.

(27) Referring to FIG. 1-16, a third resist layer 20 is formed on the first semiconductor chip 17 and the first encapsulant 19a and a plurality of openings 200 are formed in the third resist layer 20 for exposing portions of the first non-active surface 17b corresponding in position to the first electrode pads 171.

(28) Referring to FIG. 1-17, portions of the first semiconductor chip 17 under the openings 200 of the third resist layer 20 are removed to define a plurality of first through holes 170 that expose the first electrode pads 171, respectively. Further, the third resist layer 20 is removed. In another embodiment, referring to FIG. 1-17′, a third circuit layer 174 electrically connected to the first electrode pads 171 is exposed through the first through holes 170.

(29) Referring to FIG. 1-18, a first insulating layer 21 is formed on the first non-active surface 17b, the first encapsulant 19a and the first electrode pads 171. The first insulating layer 21 can be and made of Si.sub.3N.sub.4 or SiO.sub.2 through a PECVD process.

(30) Referring to FIG. 1-19, a fourth resist layer 22 is formed on the first insulating layer 21 and a plurality of openings 220 are formed in the fourth resist layer 22 to expose the first encapsulant 19a and portions of the first insulating layer 21 on the first electrode pads 171.

(31) Referring to FIG. 1-20, the portions of the first insulating layer 21 not covered by the fourth resist layer 22 are removed by etching. Then, the fourth resist layer 22 is removed.

(32) In the above-described steps of FIGS. 1-18 to 1-20, the first insulating layer 21 can be alternatively made of photosensitive benzocyclobuthene (BCB), polyimide or polybenzoxazole (PBO), which is coated, exposed and developed such that the fabrication cost is reduced and the first insulating layer 21 is elastic to absorb thermal expansion stresses in the first through holes 170 of the first semiconductor chip 17.

(33) Referring to FIG. 1-21, a third conductive layer 23 is formed on the first insulating layer 21, the first encapsulant 19a and the first electrode pads 171 so as to serve as a barrier layer and an UBM (Under Bump Metallurgy) layer.

(34) Referring to FIG. 1-22, a fifth resist layer 24 is formed on the third conductive layer 23 and a plurality of openings 240 are formed in the fifth resist layer 24 corresponding in position to the first through holes 170.

(35) Referring to FIG. 1-23, a plurality of first bumps 25a are formed in the openings 240 of the fifth resist layer 24 through electroplating, ENEPIG or solder paste print. The first bumps 25a can be made of Ni, Sn, Ag, Cu, Pd, Au, Al or a combination thereof.

(36) Referring to FIG. 1-24, the fifth resist layer 24 and the portion of the third conductive layer 23 covered by the fifth resist layer 24 are removed and the first bumps 25a are reflowed.

(37) Referring to FIG. 1-25, an electronic element such as a second semiconductor chip 26 is provided, which has a second active surface 26a with a plurality of second electrode pads 261 and a second non-active surface 26b opposite to the second active surface 26a. A copper pillar 262 and a third solder material 263 are sequentially formed on each of the second electrode pads 261.

(38) It should be noted that the steps of FIGS. 1-21 to 1-25 can be simplified as the ENEPIG process or the like so as to facilitate subsequent solder bonding with the semiconductor chip. For example, referring to FIGS. 1-21′ and 1-22′, an ENEPIG layer 175 can be formed on the first electrode pads 171 so as to dispense with the reflow process of FIG. 1-24. Further, the first electrode pads 171 can be electrically connected to the second electrode pads 261 of the second semiconductor chip 26 through the ENEPIG layer 175. Alternatively, the step of FIG. 1-23 can be replaced with an ENEPIG process or the like so as to increase solder bonding area with the semiconductor chip and dispense with the reflow process of FIG. 1-24. This can be readily understood by those skilled in the art upon reading the present disclosure and thus is not described further herein.

(39) Referring to FIG. 1-26, the second semiconductor chip 26 is disposed on the first bumps 25a of the first semiconductor chip 17 in a flip-chip manner and the steps of FIGS. 1-13 to 1-24 are repeated, thereby forming a second underfill 18b, a second encapsulant 19b, a plurality of second bumps 25b and so on.

(40) Referring to FIG. 1-27, an electronic element such as a third semiconductor chip 27 is provided, which has a third active surface 27a with a plurality of third electrode pads 271 and a third non-active surface 27b opposite to the third active surface 27a. A copper pillar 272 and a third solder material 273 are sequentially formed on each of the third electrode pads 271. It should be noted that in other embodiments, the electronic element can be a passive element or a semiconductor package.

(41) Referring to FIG. 1-28, the third semiconductor chip 27 is disposed on the second bumps 25b of the second semiconductor chip 26 in a flip-chip manner and the processes of FIGS. 1-13 to 1-14 are repeated so as to form a third underfill 18c, a third encapsulant 19c and so on.

(42) Referring to FIG. 1-29, a portion of the third encapsulant 19c is removed from the third non-active surface of the third semiconductor chip 27 by grinding. In other embodiments, the third non-active surface 27b of the third semiconductor chip 27 is exposed by grinding so as to increase the heat dissipating efficiency.

(43) Referring to FIG. 1-30, a portion of the carrier 10 is removed by grinding. If the carrier 10 is a silicon wafer, it can be removed by dry etching or chemical mechanical polishing (CMP).

(44) Referring to FIG. 1-31, the carrier 10 is completely removed by dry etching or chemical mechanical polishing (CMP) such that portions of the first conductive layer 12a are exposed to serve as bonding pads 121.

(45) Referring to FIG. 1-32, a plurality of solder balls 28 are mounted on the bonding pads 121, respectively. Alternatively, referring to FIG. 1-32′, a build-up structure is formed on the bonding pads 121 and solder balls 28 are further mounted on the build-up structure. This can be readily understood by those skilled in the art upon reading the present disclosure and thus is not described further herein.

(46) Referring to FIG. 1-33, a singulation process is performed.

(47) It should be noted that after the steps of FIG. 1-11, 1-13, 1-14, 1-15, 1-24 or 1-26, the carrier 10 can be thinned or an insulating material made of such as benzocyclobuthene (BCB), polyimide, polybenzoxazole (PBO), SiO.sub.2, Si.sub.3N.sub.4 can be coated on the carrier 10 so as to adjust surface stresses of the carrier 10, thus avoiding warpage of the overall structure.

Second Embodiment

(48) FIGS. 2-1 to 2-3 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a second embodiment of the present invention.

(49) Referring to FIG. 2-1, continued from FIG. 1-21, a fifth resist layer 24 is formed on the third conductive layer 23 and a plurality of openings 240 are formed in the fifth resist layer 24 corresponding in position to the first through holes 170 and a portion of the first non-active surface 17b. Further, a plurality of first bumps 25a and a second circuit layer 29 electrically connected to the first bumps 25a are formed in the openings 240 of the fifth resist layer 24.

(50) Referring to FIG. 2-2, the fifth resist layer 24 and the portion of the third conductive layer 23 covered by the fifth resist layer 24 are removed.

(51) Referring to FIG. 2-3, a third dielectric layer 30 is formed on the first insulating layer 21, the first encapsulant 19a and the second circuit layer 29, and a plurality of openings 300 are formed in the third dielectric layer 30 for exposing a portion of the second circuit layer 29. Further, an UBM (under bump metallurgy) layer and a second solder material 31 are sequentially formed in the openings 300 of the third dielectric layer 30. Then, semiconductor chips, passive components or semiconductor packages can be stacked on the structure as in the first embodiment.

Third Embodiment

(52) FIGS. 3-1 to 3-10 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a third embodiment of the present invention.

(53) Referring to FIG. 3-1, continued from FIG. 1-21, a fifth resist layer 24 is formed on the third conductive layer 23 and a plurality of openings 240 are formed in the fifth resist layer 24 to expose the first through holes 170, portions of the first non-active surface 17b and portions of the first encapsulant 19a.

(54) Referring to FIG. 3-2, a plurality of first bumps 25a and a heat conducting layer 32 made of such as copper are formed in the openings 240 of the fifth resist layer 24, respectively. The first bumps 25a are located in the first through holes 170 and the heat conducting layer 32 is located on the exposed portions of the first non-active surface 17b and the first encapsulant 19a.

(55) Referring to FIG. 3-3, the fifth resist layer 24 is removed.

(56) Referring to FIG. 3-4, a sixth resist layer 33 is formed to cover the heat conducting layer 32 and the first bumps 25a are exposed through a plurality of openings 330 in the sixth resist layer 33.

(57) Referring to FIG. 3-5, a plurality of third bumps 34 and a second solder material 31 are sequentially formed in the openings 330 of the sixth resist layer 33. The third bumps 34 are made of copper or nickel. The second solder material 31 is made of Sn—Ag.

(58) Referring to FIG. 3-6, the sixth resist layer 33 and the portions of the third conductive layer 23 covered by the sixth resist layer 33 are removed.

(59) Referring to FIG. 3-7, a third dielectric layer 30 is formed on the first insulating layer 21, the first encapsulant 19a and the heat conducting layer 32, and a plurality openings 300 are formed in the third dielectric layer 30 for exposing the third bumps 34, the second solder material 31 and portions of the first encapsulant 19a.

(60) Referring to FIG. 3-8, a reflow process is performed.

(61) Referring to FIG. 3-9, a second semiconductor chip 26 is provided, which has a second active surface 26a with a plurality of second electrode pads 261 and a second non-active surface 26b opposite to the second active surface 26a.

(62) Referring to FIG. 3-10, the second semiconductor chip 26 is disposed on the third bumps 34 in a flip-chip manner and further encapsulated and singulated as the first embodiment so as to form a second underfill 18b, a second encapsulant 19b, a plurality of solder balls 28 and so on. Therein, the heat conducting layer 32 is exposed from the package. Furthermore, the second underfill 18b is filled in the openings 300 of the third dielectric layer so as to increase the contact area between the second underfill 18b and the first encapsulant 19a, thereby avoiding delamination of the second underfill 18b.

Fourth Embodiment

(63) FIG. 4 is a schematic cross-sectional view showing a semiconductor package according to a fourth embodiment of the present invention.

(64) The present embodiment is similar to the third embodiment. A main difference therebetween is a thermal adhesive 35 and a U-shaped heat sink 36 are disposed outside the first encapsulant 19a, the second encapsulant 19b and the second non-active surface 26b.

(65) The heat sink 36 is connected to the heat conducting layer 32 through the thermal adhesive 35. Further, referring to FIG. 4′, a portion of the third bumps 34 is grounded so as to be connected to the heat conducting layer 32.

Fifth Embodiment

(66) FIGS. 5-1 to 5-5 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a fifth embodiment of the present invention.

(67) The present embodiment is similar to the above-described embodiments. A main difference therebetween is the carrier of the fifth embodiment is a circuit board or a packaging substrate having circuits embedded therein or on surfaces thereof and the carrier remains in the final structure.

(68) Referring to FIG. 5-1, a carrier 10 and a first semiconductor chip 17 are provided. The carrier 10 is a circuit board or a packaging substrate having circuits embedded therein or on surfaces thereof.

(69) Referring to FIG. 5-2, a first semiconductor chip 17 is disposed on the carrier 10 in a flip-chip manner. A first underfill 18a is formed between the first semiconductor chip 17 and the carrier 10. A first encapsulant 19a is formed on the carrier 10 to encapsulate the first semiconductor chip 17 and the first underfill 18a, and a portion of the first encapsulant 19a is removed from the non-active surface of the first semiconductor chip 17 by grinding.

(70) Referring to FIG. 5-3, a heat conducting layer 32 and a plurality of third bumps 34 are formed on the first semiconductor chip 17 and the first encapsulant 19a.

(71) Referring to FIG. 5-4, a second semiconductor chip 26 is disposed on the third bumps 34 in a flip-chip manner, and a second underfill 18b and a second encapsulant 19b are formed.

(72) Referring to FIG. 5-5, a portion of the second encapsulant 19b is removed by grinding, a plurality of solder balls 28 are mounted on the carrier 10 and a singulation process is performed.

Sixth Embodiment

(73) FIGS. 6-1 to 6-6 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a sixth embodiment of the present invention. Therein, FIG. 6-6′ shows another embodiment of FIG. 6-6.

(74) The present embodiment is similar to the first embodiment. A main difference of the sixth embodiment from the first embodiment is that a first conductive layer 12a and conductive elements such as a first solder material 16 or an ENEPIG layer are directly formed on the carrier 10. Then, the steps of FIGS. 1-12 to 1-31 are performed and a plurality of solder balls 28 are further mounted on the exposed portion of the first conductive layer 12a so as to form a structure of FIG. 6-6. Alternatively, referring to FIG. 6-6′, a build-up structure is formed on the exposed portions of the first conductive layer 12a and then a plurality of solder balls 28 are mounted on the build-up structure so as to form a structure of FIG. 6-6′.

Seventh Embodiment

(75) FIGS. 7-1 to 7-5 are schematic cross-sectional views showing a semiconductor package and a fabrication method thereof according to a seventh embodiment of the present invention.

(76) The present embodiment is continued from FIG. 1-11 and similar to the first embodiment. A main difference of the seventh embodiment from the first embodiment is the first semiconductor chip 17 has a plurality of first bumps 25a. The first bumps 25a can be made of copper. In subsequent processes, the first semiconductor chip 17 can be thinned from the first non-active surface 17b thereof so as to expose the first bumps 25a. Further, a fourth dielectric layer 37 is formed on the first non-active surface 17b and the first encapsulant 19a and a plurality of openings are formed in the fourth dielectric layer 37 such that the first bumps 25a are exposed through the openings so as to be electrically connected to a semiconductor chip.

(77) Alternatively, referring to FIGS. 8-1 to 8-3, only the first semiconductor chip 17 is thinned so as for the first bumps 25a to protrude above the first non-active surface 17b. Then, the fourth dielectric layer 37 is coated on the first non-active surface 17b, the first encapsulant 19a and the first bumps 25a, and a grinding process is performed to remove a portion of the first bumps 25a and the fourth dielectric layer 37 such that top ends of the first bumps 25a are exposed so as to be electrically connected to a semiconductor chip.

(78) The first semiconductor chip 17 having the first bumps 25a can further be applied to the second to sixth embodiments. This can be readily understood by those skilled in the art upon reading the present disclosure and thus is not described further herein.

(79) It should be noted that the semiconductor chips of the present invention can be bonded to other semiconductor chips or electronic elements through a solder material, a non-conductive paste (NCP), an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). In other embodiments, only an underfill or encapsulant is formed to encapsulate the semiconductor chips or electronic elements. The present invention can alternatively use stacked semiconductor chips. Further, the conductive layer can be made of, but not limited to, Ti, Cu, Ni, V, Al, W, Au or a combination thereof. In addition, the electroplated Sn—Ag can comprise Cu/Ni/Ge.

(80) The present invention further provides a semiconductor package, which has: a build-up structure having a plurality of conductive pads 131 exposed from a top surface thereof; a first semiconductor chip 17 disposed on the top surface of the build-up structure in a flip-chip manner, wherein the first semiconductor chip 17 has a first active surface 17a and a first non-active surface 17b opposite to the first active surface 17a, the first active surface 17a has a plurality of first electrode pads 171 electrically connected to the conductive pads 131, respectively, and a plurality of first through holes 170 are formed in the first semiconductor chip 17 via the non-active surface 17b thereof such that a plurality of first bumps 25a are formed in the first through holes 170 for electrically connecting the first electrode pads 171; an electronic element disposed on the first semiconductor chip 17 and electrically connected to the first bumps 25a; and an encapsulant formed on the top surface of the build-up structure for encapsulating the first semiconductor chip 17 and the electronic element.

(81) The present invention provides another semiconductor package, which has: a carrier 10 having a plurality of conductive pads 131 exposed from a top surface thereof; a first semiconductor chip 17 disposed on the top surface of the carrier 10 in a flip-chip manner, wherein the first semiconductor chip 17 has a first active surface 17a and a first non-active surface 17b opposite to the first active surface 17a, the first active surface 17a has a plurality of first electrode pads 171 electrically connected to the conductive pads 131, respectively, a plurality of first through holes 170 are formed in the first semiconductor chip 17 via first non-active surface 17b thereof such that a plurality of first bumps 25a are formed in the first through holes 170 for electrically connecting to the first electrode pads 171, and a heat conducting layer 32 is further formed on the first non-active surface 17b of the first semiconductor chip 17; an electronic element disposed on the first semiconductor chip 17 and electrically connected to the first bumps 25a; and an encapsulant formed on the top surface of the carrier 10 for encapsulating the first semiconductor chip 17 and the electronic element.

(82) In the above-described packages, the first electrode pads 171 are exposed through the first through holes 170, respectively. Alternatively, a circuit layer that is embedded in the first semiconductor chip 17 and electrically connected to the first electrode pads 171 is exposed through the first through holes 170. The first bumps can be made of one of Ni, Sn, Ag, Cu, Pd, Au, Al or a combination thereof.

(83) In the above-described packages, the build-up structure has a plurality of bonding pads 121 exposed from a bottom surface thereof, and the carrier 10 can be a circuit board or a packaging substrate.

(84) In the above-described packages, the electronic element is a semiconductor chip, a passive component or a semiconductor package. Each of the conductive pads 131 further has a second conductive layer 14 and a first solder material 16 sequentially formed thereon. A first underfill 18a is disposed between the first semiconductor chip 17 and the build-up structure, and a second underfill 18b is formed between the first semiconductor chip 17 and the second semiconductor chip 26.

(85) In the above-described packages, the encapsulant further has a first body 19a encapsulating the first semiconductor chip 17 and a second body 19b encapsulating the second semiconductor chip 26.

(86) In the above-described packages, a second semiconductor chip 26 is disposed between the first semiconductor chip 17 and the electronic element. A second circuit layer 29 is further formed on the first non-active surface 17b of the first semiconductor chip 17 and electrically connected to the first bumps 25a. The above-described package can further have a heat sink 36 attached to the encapsulant. The heat sink 36 can be U-shaped and a thermal adhesive can be disposed between the heat sink 36 and the encapsulant.

(87) In the above-described packages, the first non-active surface 17b of the first semiconductor chip 17 further has a heat conducting layer 32 formed thereon, a heat sink 36 is attached to the encapsulant and connected to the heat conducting layer 32. Therefore, the present invention performs fabrication processes directly on a carrier and eliminates the need to debond the wafer as in the prior art so as to improve the product yield. The product yield is further improved by allowing an electrical test to be performed to the carrier so as for good dies to be disposed on the carrier at positions where no electrical performance failure occurs. Furthermore, since the semiconductor chip is thinned after it is disposed on the carrier, the present invention overcomes the conventional difficulties in stacking or bonding steps. Moreover, the carrier can be removed to reduce the thickness of the overall package. In addition, a heat conducting layer and a heat sink can be provided to improve the heat dissipating efficiency.

(88) The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.