Abstract
Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
Claims
1. A method for forming an integrated circuit (IC) package, the method comprising: forming an IC package structure including a conductive terminal structure partially encapsulated by a mold compound such that a first side of the conductive terminal structure is covered by the mold compound and a second side of the conductive terminal structure opposite the first side of the conductive terminal structure has an exposed terminal structure surface; forming a first coating of a first coating material on the exposed terminal structure surface; performing a first cutting process to cut a channel extending through a full thickness of the conductive terminal structure and defining an opposing pair of terminal structure sidewall surfaces on opposite sides of the channel, each of the opposing pair of terminal structure sidewall surfaces having a full height defined by the full thickness of the conductive terminal structure; forming a second coating of a second coating material covering the full height of each of the opposing pair of terminal structure sidewall surfaces to define an opposing pair of coated terminal structure sidewall surfaces; wherein the first coating material and the second coating material comprise solder-enhancing materials; and performing a second cutting process through the channel to divide the IC package structure, wherein a second cut width of the second cutting process is smaller than a width of an opening between the opposing pair of coated terminal structure sidewall surfaces so that the second cutting process does not cut through the second coating material on the opposing pair of coated terminal structure sidewall surfaces.
2. The method of claim 1, wherein the first cutting process has a first cutting width, and the second cut width is smaller than the first cutting width.
3. The method of claim 1, further comprising, after the second cutting process to divide the IC package structure, performing a soldering process on a respective one of the coated terminal structure sidewall surfaces to form a solder having a solder connection area covering at least 80% of the full height of the respective coated terminal structure sidewall surface.
4. The method of claim 1, further comprising, after the second cutting process to divide the IC package structure, performing a soldering process on a respective one of the coated terminal structure sidewall surfaces to form a solder having a solder connection area covering at least 90% of the full height of the respective coated terminal structure sidewall surface.
5. The method of claim 1, further comprising, after the second cutting process to divide the IC package structure, performing a soldering process on a respective one of the coated terminal structure sidewall surfaces to form a solder having a solder connection area covering at least 100% of the full height of the respective coated terminal structure sidewall surface.
6. The method of claim 1, wherein the first coating material and the second coating material comprise the same material.
7. The method of claim 6, wherein the first coating material and the second coating material comprise tin.
8. The method of claim 1, wherein the first coating material and the second coating material comprise different materials.
9. The method of claim 1, wherein forming the second coating of the second coating material over the full height of each exposed terminal structure sidewall surface comprises immersing the full height of each exposed terminal structure sidewall surface in the second coating material.
10. The method of claim 1, wherein forming the second coating of the second coating material over the full height of each exposed terminal structure sidewall surface comprises performing a tin immersion process to coat the full height of each exposed terminal structure sidewall surface with tin.
11. The method of claim 1, wherein: forming the first coating of the first coating material on the exposed terminal structure surface comprises performing a tin electroplating process; and forming the second coating of the second coating material over the full height of each exposed terminal structure sidewall surface comprises performing a tin immersion process.
12. The method of claim 1, wherein each exposed terminal structure sidewall surface lies in a respective single plane.
13. The method of claim 1, wherein the IC package structure comprises a flat no-leads structure.
14. The method of claim 1, wherein the IC package structure comprises a dual flat no-leads (DFN) structure.
15. The method of claim 1, wherein the IC package structure comprises a quad flat no-leads (QFN) structure.
16. The method of claim 1, wherein the second coating of the second coating material covers the first coating material on the exposed terminal structure surface, to form a combined coating including the first coating material and the second coating material over the exposed terminal structure surface.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Example aspects and embodiments of the present disclosure are described below in conjunction with the following appended drawings:
(2) FIG. 1 shows a cross-sectional view of an example conventional QFN package;
(3) FIG. 2A shows a bottom view of a portion of a conventional QFN package after a vertical singulation cutting;
(4) FIG. 2B shows an end view of the QFN package of FIG. 2A, positioned right-side up (with the leadframe on the bottom), as viewed along direction 2B shown in FIG. 2A;
(5) FIG. 2C shows a cross-sectional side view of an edge portion of the QFN package of FIG. 2A, showing a solder connection between a leadframe terminal and underlying PCB pad;
(6) FIG. 3 shows a cross-sectional side view of an edge portion of a QFN package solder-mounted on a PCB pad, according to the prior art;
(7) FIGS. 4A-4B show an example process flow, including process steps and corresponding cross-sectional and three-dimensional views for selected process steps, for producing a group of QFN packages with notched terminals, e.g., as shown in FIG. 3, according to the prior art;
(8) FIG. 5 shows a cross-sectional view of an example conventional flat leads package, e.g., a QFP or SOT package;
(9) FIG. 6A shows a top view of a conventional flat leads package after singulation;
(10) FIG. 6B shows an end view of the flat leads package of FIG. 6A, showing four leads extending from the molded package, as viewed along direction 6B shown in FIG. 6A;
(11) FIG. 7 shows an example process flow, including process steps and corresponding three-dimensional and cross-sectional views for selected process steps, for producing a group of singulated flat leads packages, according to the prior art;
(12) FIGS. 8A-8E illustrate an example process for forming QFN packages having improved leadframe terminal wettability for improved soldering of the QFN packages to a PCB, according to an example embodiment of the present invention;
(13) FIGS. 9A-9B illustrate a more detailed example process flow for forming QFN packages having improved leadframe terminal wettability for soldering the QFN packages to a PCB, according to an example embodiment of the present invention;
(14) FIG. 10 is a table showing some example tin thickness dimensions for four example tin immersion durations, according to one example embodiment;
(15) FIG. 11 is a cross-sectional view of the end of a leadframe terminal of a QFN package produced according to the example method shown in FIGS. 9A-9B, and solder connected to an underlying PCB pad, according to one example embodiment of the invention;
(16) FIGS. 12A-12D illustrate an example process for forming flat leads packages (e.g., QFP or SOT packages) having improved lead wettability for improved soldering of the flat leads packages to a PCB, according to an example embodiment of the present invention; and
(17) FIG. 13 is a cross-sectional view of the end of a leadframe terminal of a flat leads package according to the example method shown in FIGS. 12A-12d, and solder connected to an underlying PCB pad, according to one example embodiment of the invention.
DETAILED DESCRIPTION
(18) Embodiments of the present invention provide integrated circuit (IC) packages, for example but not limited to flat no-leads packages (e.g., dual flat no-leads (DFN) or quad flat no-leads (QFN) packages) and/or flat leads packages (e.g., quad-flat packages (QFPs) and small outline transistor (SOT) packages) with improved wettable leadframe surfaces for improved solder connections between the packages and a PCB, and methods of forming such IC packages. In some embodiments the full height of each leadframe surface to be soldered to the PCB, for example—leadframe terminal sidewall surfaces in the case of flat no-leads packages, or distal end surfaces of leadframe leads in the case of flat leads packages—may be coated or otherwise covered with tin or other solder-enhancing material. As used herein, a “solder-enhancing material” refers to a material that improves or enhances a solder connection between a leadframe surface and a PCB or other structure, e.g., as compared with a solder connection between an uncoated leadframe surface and the PCB or other structure. In some embodiments a tin immersion process is performed to coat the full height of each leadframe surface to be soldered to a PCB. The solder-enhancing coating (e.g., tin) covering the full height of the leadframe surface may enhance the flow of the solder material onto the leadframe surface to form an improved solder connection between the leadframe surface and underlying PCB. For example, as discussed and shown below, the solder may form a solder fillet that extends at least 80%, at least 90%, or 100% up the height of the respective leadframe surface, to thereby provide an improved solder connection between the IC package and the PCB.
(19) FIGS. 8A-8E illustrate an example process 800 for forming flat no-leads packages having improved leadframe terminal wettability for improved soldering of the packages to a PCB, according to an example embodiment of the present invention. The no-leads packages may be DFN packages, QFN packages, or any other suitable type of packages. Each of FIGS. 8A-8E shows a cross-sectional view of each processing step (left side of the respective figure), along with a corresponding view showing the result of each processing step (right side of the respective figure).
(20) As shown in FIG. 8A, step 802 of process 800, an IC package structure 820 may be formed. IC package structure 820 may include a leadframe strip 822, a die/chip mounted on each die attach pad of the leadframe strip 822, and a mold compound 824 formed around the structure. The cross-sectional view shows a portion of the leadframe strip 822 corresponding with a pair of leadframe terminals (after subsequent processing and singulation). The corresponding “Result” image is a top view showing two rows of exposed leadframe terminal surfaces.
(21) Referring next to FIG. 8B, step 804 of process 800, the exposed top surfaces of the leadframe strip 822 may be coated with a first coating material 830, e.g., tin or other solder-enhancing material. In the illustrated example, a tin electroplating process is performed to coat the exposed top surfaces of the leadframe strip 822 with tin. The tin plating formed at 804 may have a thickness in the range of 300-1000 μinch, or other suitable thickness.
(22) It should be understood that although the explains discussed herein are largely directed to tin coatings (e.g., at steps 804 and 808 of method 800, steps 910 and 916 of method 900, and step 1206 of method 1200, any other solder-enhancing material or materials may be used to plate or coat the relevant structures in accordance with the present invention, to provide improved solder wettability and/or improved quality of solder connections.
(23) Referring next to FIG. 8C, step 806 of process 800, a wide isolation saw cut may be performed through the leadframe strip 822 to define discrete pairs of leadframe terminals 834 (one pair of terminals 834A and 834B are shown in FIG. 8C), but without cutting completely though the IC package structure 820 to singulate individual IC packages. The isolation saw cut defines exposed (copper) sidewalls of each leadframe terminal 834, indicated at 836. Unlike in certain prior art methods that form a leadframe terminal sidewall with a stepped surface, with the example method 800 (as well as example method 900 discussed below), the full surface of each exposed leadframe terminal sidewall 836 defined by the isolation saw cut may reside in a single plane, as shown in FIG. 8C.
(24) Referring next to FIG. 8D, step 808 of process 800, the exposed sidewalls 836 of the leadframe terminals 834 are coated with a second coating material 840, e.g., tin or other solder-enhancing material. The second coating material 840 may be the same as, or different, material than the first coating material 830. In some embodiments, both the first and second coating materials consist of or comprise tin. In the illustrated example, a tin immersion process is performed to coat the entire exposed surface areas of the terminal sidewalls 838. The tin immersion may also coat the first coating material 830 (e.g., tin) previously formed on the top surfaces of the leadframe strip 822 at 804.
(25) Referring next to FIG. 8E, step 810 of process 800, a saw cut singulation may be performed to singulate the structure into multiple discrete IC packages 850A, 850B (e.g., multiple discrete DFN or QFN packages). The cross-sectional view shows a pair of IC packages 850A and 850B defined by the singulation saw cut. The width of the singulation saw cut may be narrower than the isolation saw cut at 806, in order to leave the second coating material 840 (e.g., tin) intact on the leadframe terminal sidewalls 836. The corresponding “Result” images show (a) a three-dimensional view of the bottom side of one IC package 850A, and (b) an end view of a tin-coated leadframe terminal sidewalls 836 along one perimeter edge of the IC package 850A. As shown, the full height of the leadframe terminal sidewalls 836, indicated at H.sub.T, is coated with the second coating material 840, e.g., tin.
(26) In alternative embodiments, at least one solder-enhancing coating material other than tin may be applied at step 804 (electroplating) and/or step 808 (immersion). In some embodiments, different solder-enhancing coating materials may be applied at steps 804 (electroplating) and 808 (immersion).
(27) FIGS. 9A-9B illustrate another example process flow 900 for forming flat no-leads packages (e.g., DFN or QFN packages) having improved leadframe terminal wettability for soldering each IC package to a PCB, according to an example embodiment of the present invention. Process flow 900 may represent a more detailed version of the example process flow 800 shown in FIGS. 8A-8E. Figure FIGS. 9A-9B show a cross-sectional view at each step of the process 900, along with three-dimensional views of the IC structure at selected steps in the process 900.
(28) As shown in FIG. 9A, process 900 may begin with a leadframe strip 822 including a plurality of die attach pads 860 and leadframe terminal structures 862. At 902, a front-of-line (FOL) or front-end-of-line (FEOL) assembly process may be performed, including mounting an IC die/chip 864 on each die attach pad 860 and wire bonding the IC dies/chips 864 to respective leadframe terminal structures 862.
(29) At 904, the structure may be encapsulated in a mold compound 824 to define an IC package structure 820, and the IC package structure 820 may then be turned over for further processing. The mold encapsulation may be performed such that top surfaces 826 of the leadframe strip 822 are exposed through the mold 824.
(30) A post-mold cure may be performed at 906, followed by a bottom mark step to identify the package lot number by laser marking at 908. A deflash and tin electroplating process may be performed on the top side of IC package structure 820 at 910, e.g., to plate the exposed copper surfaces of leadframe strip 822 with a layer of tin 830. In some embodiment, the tin plating formed at 910 may have a thickness in the range of 300-1000 μinch, or other suitable thickness.
(31) A 2-D marking step may be performed at 912, to laser mark a 2-D matrix code and create strip mapping for use in a subsequent strip test process. At 914, a wide isolation saw cut may be performed through the leadframe strip 822 to define discrete pairs of leadframe terminals 834A and 834B separated by the wide saw cut. The isolation saw cut defines exposed (copper) sidewalls of the leadframe terminals 834, indicated at 836. Thus, unlike the prior art method shown in FIGS. 4A-4B which includes a wide saw step cut (to form a notch in the leadframe terminal structure) and a subsequent thin isolation saw cut to form “isolated” pairs of IC packages that can be strip tested, example method 900 may omit the wide saw step cut (for forming a notch) and instead perform a wide saw isolation saw cut to expose the full height of the leadframe terminal sidewalls 836.
(32) A tin immersion process may then be performed at 916, to coat the surfaces of the leadframe with tin, to thereby (a) add to the thickness of the tin plating layer 830 formed on top surfaces 826 at step 910 and (b) form a tin coating layer 840 on the leadframe terminal sidewall surfaces 836 exposed by the isolation cut at step 914. The tin immersion process may utilize any suitable parameters, e.g., temperature, time, concentration, etc., to form any desired thickness of the tin coating layer 840 on leadframe terminal sidewall surfaces 836.
(33) For example, in some embodiments, the tin immersion process may be performed using an immersion time in the range of 5 min to 2 hours; 10 min to 1 hour; 20 min to 1 hour; 30 min to 1 hour; 40 min to 1 hour; 5-20 min; 10-20 min; 15-30 min; 20-40 min; 30-50 min; or 40-50 min.
(34) In some embodiments, the tin immersion process may utilize any suitable parameters to form a tin coating layer 840 having a minimum thickness, over the area of the leadframe terminal sidewall surfaces 836, in the range of 20-150 μin; 30-100 μin; 30-80 μin; 40-100 μin; 50-100 μin; 60-100; 70-100 μin; 80-100 μin; or at least 100 μin. In some embodiments, the tin immersion process may utilize any suitable parameters to form a tin coating layer 840 having an average thickness, over the area of the leadframe terminal sidewall surfaces 836, in the range of 20-200 μin; 30-150 μin; 40-120 μin; 40-80 μin; 50-120 μin; 60-120; 70-120 μin; 80-120 μin; at least 30 μin; at least 40 μin; at least 50 μm; at least 60 μm; at least 70 μm; at least 80 μm; at least 90 μm; or at least 100 μm.
(35) FIG. 10 shows a table 1000 showing some example tin thickness dimensions for four example tin immersion durations, according to one example embodiment.
(36) After the tin immersion at 916, a strip test may be performed at 918 to test the IC packages in the strip form. A final mark may be performed at 920 to laser mark the top of the IC packages, followed by singulation saw cut at 922 to singulate the structure into multiple discrete IC packages 850A, 850B (e.g., multiple discrete DFN or QFN packages). The cross-sectional view at step 922 shows a pair of IC packages 850A and 850B defined by the singulation saw cut. In some embodiments, the width of the singulation saw cut may be narrower than the isolation saw cut at 914, in order to leave at least a portion of the tin immersion coating 840 intact on the leadframe terminal sidewalls 836. For example, the width of the singulation saw cut may be narrower than the lateral distance of the opening between the tin immersion coatings 840 on the opposing terminal sidewalls 836, to thereby leave the full thickness of the tin immersion coatings 840 intact on the leadframe terminal sidewalls 836.
(37) In alternative embodiments, at least one solder-enhancing coating material other than tin may be applied at step 910 (electroplating) and/or step 916 (immersion). In some embodiments, different solder-enhancing coating materials may be applied at steps 910 (electroplating) and 916 (immersion).
(38) FIG. 9B also shows an end view of the singulated IC package 850A after the singulation cut at step 922, which shows the sidewalls 836 of two adjacent leadframe terminals 834, coated by the tin immersion layer 840. In the illustrated example, the full height H.sub.T of each leadframe terminal 834 is coated with tin 840, in contrast with prior methods discussed above.
(39) FIG. 11 is a cross-sectional view of a portion of an electronic device including a flat no-leads package solder-mounted to a PCB, according to one embodiment. In particular, FIG. 11 shows the end of one leadframe terminal 834 of the no-leads package, produced according to the example method 800 shown in FIGS. 9A-9B, solder connected to an underlying PCB pad 880, according to one example embodiment of the invention. As shown, the bottom surface 826 and sidewall surface 836 of the leadframe terminal 834 have been coated with tin to enhance the solder connection. In particular, bottom surface 826 may be coated by a tin plating layer 830 (steps 804, 910 discussed above) and tin immersion layer 840 (steps 808, 516 discussed above), while terminal sidewall surface 836 is coated by the tin immersion layer 840 (steps 808, 916 discussed above). As shown, the full height H.sub.T of the terminal sidewall surface 836 may be coated with tin 840, to enhance the solder wetting and/or quality of a resulting solder connection. As discussed above, providing the tin coating 840 on the full height of the terminal sidewall 836 may enhance the flow of the solder material to form a solder fillet 890 that extends at least 80%, at least 90%, or 100% up the full height H.sub.T of the terminal sidewall surface 836, to thereby provide improved solder wettability and/or improved solder connection. In the example shown in FIG. 11, the resulting solder fillet extends 100% up the height H.sub.T of the terminal sidewall surface 836.
(40) In addition to the disclosed techniques for forming flat no-leads packages, e.g., QFN packages, having improved lead wettability for improved soldering, the inventors have also developed inventive techniques for forming flat leads packages, e.g., QFP or SOT packages, having improved lead wettability for improved soldering.
(41) FIGS. 12A-12D illustrate an example process 1200 for forming flat leads packages, e.g., QFP or SOT packages, having improved lead wettability for improved soldering of the flat leads packages to a PCB, according to an example embodiment of the present invention. Each of FIGS. 12A-12D shows a cross-sectional view of each processing step (left side of the respective figure), along with a corresponding view or views showing the result of each processing step (right side of the respective figure).
(42) As shown in FIG. 12A, step 1202 of process 1200, an IC package structure 1220 may be formed. IC package structure 1220 may include an array of dies/chips, each mounted on a respective die attach pad (DAP) of a common leadframe, and each mounted die/chip being encapsulated by molding compound to define an array of encapsulated IC structures. FIG. 12A, step 1202, shows two of such encapsulated IC structures 1226A and 1226B, each including a mounted die/chip encapsulated by a mold compound 1224, and both formed on a common leadframe 1222. As shown, exposed portions of the leadframe 1222 extend between adjacent encapsulated IC structures. Step 1202 may correspond with the Assembly FOL and Encapsulation steps of the process shown in FIG. 7.
(43) Next, as shown in FIG. 12B, a lead isolation step may be performed at step 1204, in which the leadframe 1220 is cut at selected locations (and through the full height/thickness of the leadframe) to electrically isolate individual encapsulated IC structures or subsets of encapsulated IC structures from each other, to allow operational testing of the various IC structures. The isolation cutting process may leave other selected portions of the leadframe 1220 uncut, such that the electrically isolated IC structures remain physically connected to each other. The isolation cutting process may define a group of leads 1232 extending from opposing lateral sides of each encapsulated IC structure, such that the cut distal end of each lead 1232 defines an exposed end surface 1234. The cross-sectional view (left side) shows selected isolation cut lines that isolate the encapsulated IC structure 1226A and define leads 1232 extending from opposing lateral sides of the encapsulated IC structure 1226A. As shown, the isolation cuts define an exposed end surface 1234 at the distal end of each lead 1232. The corresponding top view (right side) shows isolation cuts through the leadframe 1220 that isolate encapsulated IC structures 1226A and 1226B, and define leads 1232 extending from each encapsulated IC structure 1226A and 1226B.
(44) As shown in FIG. 12C, a coating immersion step may be performed at step 1206, in which the leadframe including the array of encapsulated IC structure is immersed in or otherwise fully exposed to a solder-enhancing material to thereby coat the exposed surfaces of the leadframe 1220, including top, bottom, and side surface of each lead 1232 extending from each mold-encapsulated IC structure. In the illustrated example, the solder-enhancing material comprises tin, and thus step 1206 may referred to as a tin immersion. In other embodiments, the solder-enhancing material may comprise any other material that enhances solder wettability or otherwise improves the creation, strength, or other quality of a solder connection between the respective lead 1232 and a PCB or other structure to which the respective IC structure is mounted.
(45) The cross-sectional view (left side) shows the solder-enhancing coating 1240 on the exposed leadframe surfaces of IC structure 1226A. As shown, all exposed surfaces of each lead 1232, including the distal end surface 1234 of each lead 1232, are coated by solder-enhancing coating 1240, unlike in a conventional process in which the distal end surfaces of the leads remain uncoated. The tin-coated leads 1232 are indicated at 1242. In one embodiment solder-enhancing coating 1240 comprises tin.
(46) The corresponding top view (right side) shows the result of the tin immersion process on IC structures 1226A and 1226B, including tin-coated leads 1242 extending from IC structures 1226A and 1226B. In addition, to the cross-sectional view and top view discussed above, FIG. 12C includes an end view along the direction labelled EV in the top view. The end view shows the distal ends of the four tin-coated leads 1242 extending from one side of the mold-encapsulated IC structure 1226A. As shown in the end view, the distal end of each lead 1242, including the distal end surface 1234 of the lead 1242, is coated by solder-enhancing coating 1240. In this embodiment, the entire surface area of the distal end surface 1234 of each lead 1232 is coated with tin by the tin immersion process, which may improve solder wettability and/or solder quality for solder connecting the leads 1232 to a PCB, as discussed below.
(47) After the tin immersion step, a strip test, as described in relation to FIG. 7, may be performed to electrically test the IC structures while they are isolated from each other but still physically connected to the common leadframe.
(48) As shown in FIG. 12D, lead forming and singulation processes may be performed at step 1208, in which the (a) the tin-coated leads 1242 extending from each IC structure are formed, for example by physically bending/deforming the tin-coated leads 1242 downwardly toward the bottom surface of the respective IC structure, and (b) the IC structures are singulated from each other by a singulation cutting process, to thereby define a group of formed and singulated IC devices 1250 having tin-coated leads 1242. The singulation cutting process may include cutting the leadframe 1120 at locations that were not cut during the isolation cutting process, e.g., at locations distinct from the leadframe leads 1232 defined by the isolation cutting process. Thus, the singulation cutting process does not remove the tin coating on the lead 1232, such that the distal ends of the leads 1232 (including the distal end surfaces 1234) remain fully tin-coated after singulation of the IC structures.
(49) The IC device 1250 shown in FIG. 12D represents the IC structure 1226A shown in FIG. 12C after the lead forming and singulation process at step 1208. FIG. 12D includes an end view along the direction labelled EV in the top view, which shows the distal ends of the four tin-coated leads 1242 extending from one side of the singulated IC device 1250. As shown in the end view, the distal end of each tin-coated lead 1242 is fully covered by the solder-enhancing coating 1240. As discussed above, using a tin immersion process to provide tin-coating of the entire distal end of each lead 1242 (including the full surface area of the distal end surface 1234) may improve solder wettability and/or solder quality for solder connecting the leads 1242 to a PCB or other structure to which the IC device 1250 may be mounted.
(50) FIG. 13 is a cross-sectional view of a portion of an electronic device including a flat leads package solder-mounted to a PCB, according to one embodiment. In particular, FIG. 13 shows the tin-coated distal end of one leadframe lead 1232 of the flat leads package, produced according to the example method 1200 shown in FIGS. 12A-12D, solder connected to an underlying PCB pad 1280, according to one example embodiment of the invention. As shown, all surfaces of the leadframe lead 1232, including the full surface area of the distal end surface 1234, have been coated with solder-enhancing tin coating 1240 by a tin immersion process (see step 1206, discussed above) to enhance the solder connection. As discussed above, tin-coating the entire distal end of the lead 1232 may enhance the flow of the solder material to form a solder fillet 1290 that extends at least 80%, at least 90%, or 100% up the full height H.sub.T of the distal end surface 1234 of the lead 1232, to thereby provide improved solder wettability and/or improved solder connection. In the example shown in FIG. 13, the resulting solder fillet extends 100% up the height H.sub.T of the distal end surface 1234 of the lead 1232.
