Power FET with a resonant transistor gate

Abstract

A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

Claims

1. A semiconductor FET, comprising a resonant gate electrode that modulates transconductance between source and drain electrodes, wherein: a plurality of passive circuit elements including one or more inductor elements are embedded within the structure of the gate electrode that causes the gate electrode to respond electrically as a resonant transmission line; and, said resonant transmission line further consists of one or more resonant transmission line segments that are in turn connected in series to operate as a distributed network filter, such that, the semiconductor FET modulates transconductance at a resonant frequency or resonant frequency band characteristic to each resonant transmission line segment forming the distributed network filter.

2. The semiconductor FET of claim 1, wherein the passive circuit elements embedded within the structure of the gate electrode to form the distributed network filter are electrically connected in series or in parallel.

3. The semiconductor FET of claim 1, wherein the resonant gate electrode comprises a serpentine path and the passive circuit elements are formed by localized reactive loading within regions along the serpentine path is generated by the electromagnetic coupling between parallel or anti-parallel alignment of instantaneous current vectors flowing between adjacent portions of serpentine path.

4. The passive circuit elements of claim 3, wherein electroceramic elements are incorporated within the regions of localized coupling.

5. The passive elements of claim 4, wherein the electroceramic elements comprise high dielectric density electroceramic with relative permeability .sub.r10 or relative permittivity .sub.r10.

6. The semiconductor FET of claim 2, wherein the embedded passive circuit elements are discrete dielectric passive circuits elements comprising an electroceramic element forming a resistive element, a capacitive element, or an inductive element.

7. The capacitive electroceramic elements of claim 6, wherein capacitive electroceramic elements comprise a high energy density electroceramic with relative permittivity .sub.r10.

8. The inductive electroceramic elements of claim 6, wherein the inductive electroceramic elements comprise a high energy density electroceramic with relative permeability .sub.r10.

9. The inductive electroceramic elements of claim 6, wherein the inductive element is a toroidal inductor, a spiral inductor, or a curved current path.

10. The semiconductor FET of claim 1, wherein a resonant transmission line segment forming the distributed network filter comprises a resistive element that tunes the resonant transmission line segment to be critically dampened at a characteristic frequency or frequency band.

11. The semiconductor FET of claim 1, wherein a resonant transmission line segment forming the distributed network filter comprises a terminal resistive element that broadens the frequency bandwidth of the resonant transmission line segment.

12. The semiconductor FET of claim 1 configured as a vertical FET or surface FET.

13. The semiconductor FET of claim 1 formed on silicon, silicon germanium, III-V compound or II-VI compound semiconductor.

14. The semiconductor FET of claim 1 embedded within a power management module.

15. The semiconductor FET of claim 14, wherein the power management module is a monolithic power management module.

16. The semiconductor FET of claim 1 that comprises an elongated gate width (W.sub.gate) wherein the ratio of gate width to gate length (L.sub.gate) is W.sub.gate/L.sub.gate10.sup.2, preferably W.sub.gate/L.sub.gate10.sup.6.

17. The power management module of claim 14, wherein the semiconductor FET comprises a resonant gate electrode that has a frequency bandwidth that has a resonant frequency or resonant frequency band that overlaps the frequencies of interest to the control topology.

18. The power management module of claim 14 incorporated within an electric motor, radio base station, power distribution network or handheld wireless appliance.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention is illustratively shown and described in reference to the accompanying drawings, in which:

(2) FIGS. 1A,1B,1C,1D illustrate the physical design of a monolithic power management module modulated by a resonant gate surface FET having dielectric passive components embedded within the resonant gate used to form an RLC circuit and a schematic for the RLC circuit depicted in the physical models.

(3) FIGS. 2A,2B,2C illustrate the physical design of a monolithic power management module modulated by a resonant gate surface FET having dielectric passive components embedded within the resonant gate to form an RLC circuit.

(4) FIGS. 3A,3B,3C,3D,3E,3F,3G depict various circuit elements used to form a resonant gate transistor.

(5) FIGS. 4A,4B provide electrical circuit schematics of RLC circuits formed using passive components configured in series and in parallel.

(6) FIGS. 5A,5B,5C,5D,5E,5F illustrate the physical design of a monolithic power management module modulated by a dielectrically loaded serpentine resonant gate transistor and a schematic for the RLC circuit depicted in the physical models.

(7) FIG. 6 illustrate a semiconductor carrier comprising a monolithic power management module modulated by a resonant gate transistor formed by embedding dielectric load materials within resonant transistor gate.

DESCRIPTION OF THE PREFERRED EMBODIMENT

(8) This application is copending with de Rochemont U.S. Ser. No. 13/168,922, entitled SEMICONDUCTOR CARRIER WITH VERTICAL FET POWER MODULE, filed Jun. 24, 2011 (de Rochemont '922), and de Rochemont U.S. Ser. No. 13/163,654, entitled FREQUENCY-SELECTIVE DIPOLE ANTENNA, filed Jun. 17, 2011 (de Rochemont '654), which are incorporated herein by reference. The current application instructs the incorporation of passive components and/or high dielectric density electroceramic elements within transistor gate structures to cause a power FET to become resonant at a desired frequency or range of desired frequencies. One counterpart application (de Rochemont '922) instructs means to fully integrate a high efficiency, power management system as a monolithic structure on a semiconductor carrier to modulate high current levels using a resonant three-dimensional gate structure enabled by serpentine windings. The other counterpart application, (de Rochemont '654), instructs methods to form a conducting element as a serpentine winding by folding the conducting element in ways that introduce localized regions of capacitive or inductive loading, such that the combination of localized reactive loads along the length of the folded conductor form a distributed network filter. It goes on to illustrate how two mirror image serpentine elements so formed function as a dipole antenna that is resonant over selective frequencies. The counterpart application de Rochemont '654 also instructs the insertion of tight-tolerance electroceramic material within the regions of localized reactive loading to increase or more precisely tune the coupling strength of localized reactive loads. The current application is also copending with de Rochemont U.S. provisional application No. 61/409,846, QUANTUM DOT FIELD EFFECT TRANSISTOR IN A FULLY INTEGRATED SILICON CARRIER AND METHOD OF MANUFACTURE THEREOF, filed Nov. 3, 2010 (de Rochemont '846), which is incorporated herein by reference.

(9) The current application incorporates by reference all matter contained in de Rochemont, U.S. patent application Ser. No. 11/479,159, filed Jun. 30, 2006, entitled ELECTRICAL COMPONENT AND METHOD OF MANUFACTURE (the '159 application), de Rochemont, U.S. patent application Ser. No. 11/620,042 filed Jan. 6, 2007 entitled POWER MANAGEMENT MODULES (the '042 application, de Rochemont and Kovacs, U.S. patent application Ser. No. 12/843,112 filed Jul. 26, 2010, LIQUID CHEMICAL DEPOSITION PROCESS APPARATUS AND EMBODIMENTS, (the '112 application), and de Rochemont U.S. patent application Ser. No. 13/152,222, entitled MONOLITHIC DC/DC POWER MANAGEMENT MODULE WITH SURFACE FET, filed Jun. 2, 2011 (the '222 application). The '159 application discloses how LCD methods fabricate a monolithic integrated circuit comprising tight tolerance passive networks. The '042 application discloses how liquid chemical deposition (LCD) methods fabricate a monolithic integrated power management module that includes a tunable inductor coil. The '112 application discloses preferred apparatus used in applying LCD methods. The '222 application instructs the monolithic integration of a low-loss power management circuit containing a surface FET.

(10) The present invention applies LCD manufacturing methods to integrate tight-tolerance passive circuit elements within the gate structure of a field effect transistor to produce a resonant gate signal response at a desired frequency or band of frequencies. The modulation of large currents typically requires large gate structures that increase gate capacitance, which, in turn, decreases switching speed. Large gate structures can be switched at higher speeds by applying more energy to the gate to displace the charge that collects underneath it. However, the displacement of large quantities of electrical charge under a large gate will require more energy to be applied to the gate electrode than is passed from the source to the drain to achieve the switching speeds desired in many modern microelectronic applications. This paradox results in negative efficiency devices. It is a specific objective of the present invention to modulate FET power output at arbitrarily high frequencies (switching speeds) in FETs having arbitrarily large gate structures. It is an additional objective to produce high-speed/high-current power management devices by embedding resistive, capacitive and inductive elements to form an RLC circuit within the gate enable the transistor gate to be operated under conditions of gate resonance. At gate resonance the switching response is effortless because the embedded inductance neutralizes the reactance of the gate and any embedded capacitors. As discussed further below, the passive circuit elements embedded within the gate structure are used to tune the gate's resonant frequency response to match any desired switching speed or band of switching frequencies regardless of the gate's surface area and internal capacitance. This resonant frequency response is achieved by embedding tight-tolerance, high-density dielectric materials that precisely tune the performance values of the embedded passive circuit elements located at select locations within the gate structure. The resonant transistor gate thereby allows power FET to manage arbitrarily large currents, limited only by the resistance and patterning of the conductors within in the device. The shape and elemental chemistry of the device conductor elements should selected to minimize resistive loss and electromigration to ensure reliable operation.

(11) LCD manufacturing methods allow compositionally complex and mismatched materials having atomic-scale chemical uniformity and stoichiometric precision to be integrated in selected areas on the surface of a semiconductor substrate. The process temperatures (400 C.) used by LCD do not alter dopant profiles of active components buried within the semiconductor substrate. These low deposition temperatures also allow the microstructure of LCD deposits to be restricted to nanoscale dimensions. Nanoscale microstructural controls are a necessary condition for producing electroceramic compositions that have functional properties that remain stable with varying temperature. These combined attributes allow complex electroceramics to be formed into higher performance passive components that hold the critical performance tolerances needed to make passive circuit integration economically viable. LCD manufacturing technology enables monolithic integration of passive components by ensuring their operational performance values are held to within 1% of their desired performance over standard operating temperatures without disturbing active circuitry embedded within a semiconductor substrate.

(12) The invention relates primarily to the formation of a resonant transistor gate structure fabricated by placing electroceramics as a passive component or a dielectric element on the surface of a semiconductor. The invention is not dependent on a particular doping structure within the semiconductor substrate and can be applied to any and all currently known FET junction doping patterns or any contemplated power FET doping structures without limitation to marginal gains that might be achieved by one doping profile relative to another when applied to a specific application.

(13) Reference is now made to FIGS. 1A,1B,1C,1D & 2A,2B,2C to illustrate the principal embodiments of the invention. FIGS. 1A,1B,1C depict a monolithic power management module 1 that consists of a toroidal inductor or transformer coil 3, a controller circuit 5, a embedded diode 7 and an output capacitor 9 formed on the surface of a p-type semiconductor 10 using similar methods to those described in the '222 application. In this particular instance, a resonant gate surface FET 11 modulates current flow between the source electrode 13 and the drain electrode 15. The source electrode is in electrical communication with the transformer coil 3. The drain electrode 15 contacts electrical ground on the backside of the p-type semicondcutor 10 through a thru via 16. The resonant gate surface FET 11 is produced by forming surface gate structure segments 19 between and above n-type source 21 and drain 23 diffusion regions embedded within the p-type semicondcutor 10 upon which the monolithic structure is formed. Voltage applied to the gate electrode 25 forms a conductive channel 27 in the p-type semicondcutor 10 immediately below the gate insulator 29, which allows current to pass between the n-type source 21 and drain 23 diffusion regions. LCD methods are used to embed passive components comprising one or more embedded resistor elements 31, embedded capacitor elements 33, and embedded inductor elements 35 that are introduced between surface gate structure segments 19. Although depicted in series connection, the embedded passive components may be formed in series and/or in parallel with one another with the surface gate structure segments 19 as needed by a given design. The embedded passive components (31,33,35) in combination the surface gate structure segments 19 are used to transform the gate into a resonant transmission line. The gate signal frequency response is tuned by selecting a combination of passive component (31,33,35) values using RLC lumped circuit or distributed network filter techniques to cause the gate signal to be resonant at a desired frequency or range of frequencies. Surface gate structure segments 19 that modulate current between the source 13 and drain 15 electrodes, such as that shown in A-A cross-section in FIG. 1B, are treated as capacitive elements in the lumped RLC circuit analysis. FIG. 1D provides a circuit schematic of the resonant gate surface FET 11 illustrated in FIG. 1C to show how the gate structure segments 19A,19B,19C and the various embedded passive components (31,33,35) form a transmission line 40 when they are electrically interconnected in series. The resonant transmission line 40 may consist of one or more resonant transmission line segments 42A,42B,42C,42D that are in turn electrically connected in series. As discussed in greater detail below, the resonant characteristics can be more simply derived using closed equations if gate structure segment 19C is omitted from the circuit, and circuit elements 19A,19B&33 are reduced to a single lumped capacitor.

(14) The resonant gate surface FET 11 need not be formed using a series-connected resonant transmission line 40 as shown in FIG. 1D. As illustrated in greater detail below, resonant transmission lines can also be formed by connecting various embedded passive components (31,33,35) in parallel. Such connections would be made by placing one electrode of the various embedded passive components (31,33,35) in electrical contact with source electrode 13 or each other, with the remaining electrode making electrical contact with a gate structure segment 19. It is herein understood that present invention covers all possible configurations that electrically connect embedded passive components (31,33,35) in series or in parallel that form a resonant transmission line or resonant transmission line segment.

(15) FIGS. 2A,2B,2C depict an alternative monolithic power management module 50 that consists of a toroidal inductor or transformer coil 51, a controller circuit 53, an embedded diode 55 and an output capacitor 57 formed on an electronically patterned multilayer semiconductor 58 using methods similar to those described in de Rochemont '922. In this instance, a resonant gate vertical FET 59, located beneath and insulated from the source electrode 63 modulates current flow between a drain electrode 61 and the source electrode 63. The source electrode 63 is in electrical communication with the transformer coil 51. FIG. 2B depicts a close-up top view of the resonant gate vertical FET 59 with the source electrode 63 removed for illustrative clarity. The resonant gate vertical FET 59 is formed by inserting passive components (resistors 65, capacitors 67, 69, and/or inductors 71) between vertical gate structure segments 72. Vertical gate structure segments 72 are shown in cross-sectional view B-B in FIG. 2C. All elements of the resonant gate vertical FET 59 are electrically insulated from the source electrode 63 by an amorphous silica encapsulant, (not shown for illustrative clarity), unless a ground contact to a passive component is called for as discussed below. The vertical gate structure segment 72 may also be placed between multiple parallel source electrodes in configurations where the source electrode 63 does not overlay the gate structure (not shown).

(16) In general, a vertical FET consists of a drain electrode 61, a drain layer 73 comprising a highly doped semiconductor material, (usually doped with charge carrier densities in the range of 10.sup.18 to >10.sup.19 cm.sup.3), and a lightly doped (usually n-type) intrinsic semiconductor layer 75 having charge carrier density in the range of 10.sup.10 to <10.sup.17 cm.sup.3 depending upon the semiconductor material and design considerations. The intrinsic semiconductor layer 75 will be selectively doped with opposite type (usually p-type) dopants in barrier diffusion regions 77 to produce active junctions. The diffusion regions 77 may be trenched or take the form of pillars used to form a superjunction (not shown) as design alternatives. Similarly, the drain layer 73 may be n-type to form a conventional double-diffused junction (DDMOSFET) or may be p-type to form an insulated gate bipolar transistor (IGBT). Source diffusion regions 79 (usually n.sup.+-type with charge carrier density >10.sup.17 cm.sup.3) are formed to establish ohmic contact with the source electrode 63. Voltage applied to the gate electrode 81 forms a conductive channel 83 within the barrier diffusion regions 77 immediately below the gate insulator 84 of the gate structure segment 72 to modulate current flow 85 between the source electrode 63 and drain layer 73.

(17) In a resonant gate vertical FET 59, LCD methods are used to insert passive components comprising one or more resistor elements 65, capacitor elements 67,69, and inductor elements 71 at select locations between the vertical gate structure segments 72. Performance values of the passive components and their electrical interconnection, whether in series or in parallel, are selected using methods of RLC lumped circuit or distributed network filter analysis to cause the gate to operate as a resonant transmission line having frequency response optimized (resonant) at a desired frequency or band of frequencies. Vertical gate structure segments 72 that modulate current between the source electrode 63 and drain layer 73, such as that shown in B-B cross-section in FIG. 2C, are treated as capacitive elements in the lumped RLC circuit/distributed network analysis. The vertical gate structure segments 72 and the inserted passive components 65,67,69,71 are normally encapsulated with an insulating material, preferably amorphous silica insulator, which is not depicted in the figures for purposes of illustrative clarity. Furthermore, although passive components 65,67,69,71 are depicted as series elements located at equal angles of arc for visual simplicity, most functional designs will require the passive components 65,67,69,71 to be configured in series and/or in parallel and spaced with the resonant gate vertical FET 59 at consistent units of arclength. The resonant characteristics of the resonant gate vertical FET 59 would be determined using similar methods to those depicted in FIG. 1D and discussed in greater detail below.

(18) Reference is now made to FIGS. 3A-3G to better illustrate the passive components that form the resonant gate FETs 11,59. Each gate structure segment 19,72 of the resonant gate transistor is modeled as an active series capacitor. This is depicted in FIG. 3A, where the active series capacitor 100 consists of a conductive gate electrode 102 separated from the electrically patterned semiconductor surface 104, which comprises the bottom electrode, by a gate oxide 106. The active series capacitor 100 is added in series to one or more passive series capacitors 33,67. A suitable construction for an embedded series capacitor 110 is depicted in FIG. 3B. The embedded series capacitor 110 has a performance value selected to minimize the input capacitance of the resonant gate transistors 11,59 and to match other design objectives. The embedded series capacitor 110 has an upper electrode 112 that is in electrical communication with the conductive gate electrode 102A of the active series capacitor 100. The upper electrode 112 is separated from a lower electrode 114 by a tight tolerance dielectric material 116. The lower electrode 112 is in electrical communication with the conductive gate electrode 102B of the next active series capacitor 100 in resonant gate transistors 11,59 or, as the design warrants to another passive component or conducting element forming the resonant circuit. Although FIG. 2B depicts the series capacitors 67 in the resonant gate vertical FET 59 as elements that are used to electrically connect an outer circumferential portion of an arcuate gate electrode with an inner circumferential segment, any of the passive tuning elements or a portion of the active series capacitor 100 may be used to connect an outer circumferential segment with an inner circumferential segment of the resonant gate transistor.

(19) Certain design criteria may require embedded parallel capacitors 120, (shown in FIG. 3C), to be added within the resonant gate FETs 11,59. Embedded parallel capacitors 120 are constructed by depositing a signal electrode 122 that is in electrical communication with the gate electrode 124 of an active series capacitor 100. In a resonant gate vertical FET 59, a ground electrode 125 has an exposed portion 126 that has no encapsulating dielectric (not shown) so as to be in electrical contact with the overlaid source electrode 63 that simultaneously functions as an electrical ground. The ground electrode 125 is directly connected to the source electrode in a resonant gate surface FET 11. The signal electrode 122 is separated from a ground electrode 126 by a tight tolerance dielectric material 128. Similar methods would be used to make parallel connections with resistive elements 27,65 or inductor elements 31,71 or other capacitive elements 67 embedded with the resonant gate transistors 11,59 as a particular design may require. The ground electrode 126 may optionally be in electrical communication with other elements of the resonant gate transistor 11,59.

(20) Representative embedded inductor elements 31,71, (shown in FIGS. 3D & 3E), may comprise an embedded coil 130 consisting of windings 132 wound around a magnetic core dielectric 134. Opposite ends of the windings are in electrical communication with gate electrodes 136A,136B of an active series capacitor, or other passive components or ground electrodes when connected in parallel as a specific design might warrant. Alternatively, embedded inductor elements 31,71 may comprise embedded linear or spiral inductors 140 consisting of curved conductor segments 142 deposited upon the patterned semiconductor 143. The linear or spiral embedded inductors 140 may optionally be placed on a dielectric material 144 that may or may not be a magnetic dielectric. Opposing ends of the linear or spiral inductor maintains electrical communication with the electrodes 146A,146B of an active series capacitor, or other passive components or ground electrodes when connected in parallel as a specific design might warrant.

(21) Representative embedded resistive elements 150 (shown in FIG. 3F) will generally consist of electrodes 152A,152B in electrical communication with gate electrodes 1546A,154B of an active series capacitor, or other passive components or ground electrodes when connected in parallel as a specific design might warrant. The electrodes 152A,152B are separated by a resistive dielectric element 156, preferably composed of a tight-tolerance resistive material.

(22) For reasons relating to the critical dampening of the transistor's resonant response discussed below, it is a preferred embodiment of the invention to configure a resistive component as an embedded terminating resistor 160 as shown in FIG. 3G. The embedded terminating resistor 160 comprises an electrode 162 that is in electrical communication with the gate electrode 37,87 of a gate structure segment 19,71 and a resistive element 164, preferably a tight tolerance electroceramic resistive element, inserted between the electrode 162 and a terminating electrode 166. As is the case with all elements of the resonant gate transistor and power management modules derived therefrom, the terminating resistor may be encapsulated by an insulator (not shown for visual clarity), preferably an amorphous silica insulator. Therefore, the terminating electrode 166 should also contain an exposed surface 168 that makes electrical contact with the overlaid source electrode 63 of a resonant gate vertical FET 59. Alternatively, the exposed surface 168 would make direct electrical contact with the source electrode 13 in a resonant gate surface FET 11 device.

(23) It is further recommended that barrier layers (not shown) be inserted between the passive components' dielectric material and the semiconductor substrate to prevent migration of any element within the dielectric material that might readily diffuse into the semiconductor while operating the device.

(24) On resistance is a critical operational parameter of all power FETs, since higher resistivity generates more heat, which, if not properly managed, will produce higher temperatures in the channel region that will degrade transistor performance. The On resistance (R.sub.ON) of a standard vertical FET is the sum of the channel resistance (R.sub.Ch) and the drain resistance (R.sub.Drain) and is mathematically characterized using:

(25) $\begin{array}{cc}{R}_{\mathrm{ON}}=R_{\mathrm{Ch}}+R_{\mathrm{Drain}}& \left(1a\right)\\ =\frac{L_{\mathrm{gate}}}{W_{\mathrm{gate}}{C}_{\mathrm{gate}}{\mathrm{.Math.}}_{\mathrm{elec}}\left(V_G-V_{\mathrm{GS}\left(\mathrm{sh}\right)}\right)}+{}_{\mathrm{Drain}}& \left(1b\right)\end{array}$ Where, L.sub.gate is gate length, W.sub.gate is the gate width, C.sub.gate is the gate capacitance, .sub.elec is the electron mobility of the intrinsic semiconductor layer 68, VG and VGS(sh) are the gate and short-circuited gate-source voltages, respectively, k is a geometrical factor related to electrode geometries, and, .sub.Drain is resistivity of the intrinsic semiconductor layer 68 and the drain layer 69 added in series. The gate length L.sub.gate, when viewed in cross-section, is the width of the gate electrode 87 (37 in the case of a surface FET) as depicted in FIG. 2C (FIG. 1B). Similarly, the gate width, W.sub.gate, would extend above and below the plane in the cross-sectional view provided in FIGS. 1B, & 2C, and is the sum total of the combined widths of all the active gate structure segments 72 (19) contained within the resonant transistor gate. The present invention reduces R.sub.ON in two significant ways. An elongated gate width can be wound circumferentially within the donut hole of the inductor or toroidal coil 3,51. Each arcuate segment of the resonant gate vertical FET 59 wound within an outer circumferential region can be electrically connected to an interior arcuate segment. Resonant action within gate allows extreme elongated gates to be configured in this manner, so it is an aspect of the invention to have at least one, preferably more than one, circumferential loop forming the resonant gate vertical FET 59. The gate structure segments 19,72 are naturally formed over circumferential patterned doping profiles implanted or diffused into the semiconductor substrate layer.

(26) This model representation of the present invention depicts a FET gate electrode that has a 30 m gate length (L.sub.gate) and a 1 meter wide gate width (W.sub.gate) to make it easier to visualize pictorially. It could just as easily comprise an FET gate electrode that a 1 m long (or smaller) gate length (L.sub.gate) and a 30 meter wide (or wider) gate width (W.sub.gate). A specific embodiment of the invention is to establish a gate electrode structure wherein the gate width (W.sub.gate) is at least two orders of magnitude, preferably more than 6 orders of magnitude, greater than the gate length (L.sub.gate). i.e., 10.sup.2W.sub.gate/L.sub.gate, preferably 10.sup.6W.sub.gate/L.sub.gate. Making reference to equations 1a, 1b, it is quite evident that the gate geometry described within the present invention enables a substantial reduction in On Resistance (R.sub.ON) by reducing its channel resistance (R.sub.Ch) component, which is inversely proportional to the ratio W.sub.gate/L.sub.gate. For example, a gate geometry wherein W.sub.gate/L.sub.gate is 10.sup.6 will have 1 1/millionth the channel resistance of a gate electrode where W.sub.gate/L.sub.gate=1. There are corresponding reductions in the drain resistance R.sub.Drain, since the geometrical factor, k, for the source electrode 63 is the ratio of the thickness of the intrinsic semiconductor layer 75 to the source electrode surface area. When there is a donut hole (not shown) at the center of the source electrode 63, its total surface area is determined as the area spanned by the outer radius minus the area spanned by the inner radius, or:
A=(R.sub.out.sup.2R.sub.in.sup.2)(2)
where, R.sub.in=0 when there is no hole at the center. Ordinarily, the thickness of the intrinsic semiconductor layer 75 is 5 m (510.sup.4 cm) or less. When the source electrode has an outer radius on the order of 1 cm with an inner radius of 0.4 cm, the total surface area of the donut is 2.51 cm.sup.2 making the geometrical factor k=210.sup.4, assuming an intrinsic semiconductor 75 layer thickness of 5 m. In designs where the layer thickness can be reduced to 2 m and the source electrode is expanded to 2 cm radius with no donut hole, the geometrical factor becomes k=1.610.sup.5. Consequently, the greatly expanded size of the source electrode 63 that is enabled adding greater economic value to the semiconductor real estate by fully integrating the entire system onto the semiconductor dramatically reduces the On Resistance (R.sub.ON). The expanded source electrode, and the elongated gate widths underneath it, reduces loss in the system, thereby mitigating the need for additional system costs, such as coolant loops, to be incorporated into the larger system. The greater overall efficiency of this one fully integrated circuit lowers the cost and improves the intrinsic value of diverse systems, such as an electric motor, a radio base station, or power distribution network, in which the power management system may ultimately be applied. These concepts may also be applied to lower power systems, such as handheld wireless appliances, by shrinking the scale of the device to match the lower power requirement of those systems.

(27) A drawback to elongated gate widths is that they will also have higher gate capacitance (C.sub.gate). While higher gate capacitance reduces channel resistance R.sub.Ch, the higher gate capacitance C.sub.gate also reduces the gate switching speed. Lower gate switching speeds are undesirable since they require larger inductance and capacitance values to be integrated into circuit, necessitating the integration of large scale components. Therefore, an additional aspect of the present invention is to integrate tight tolerance LCD passive components in series or in parallel into that gate electrode to minimize the gate input capacitance C.sub.INgate, while maintaining elongated gate widths, C.sub.gate. As explained in greater depth below, gate input capacitance can be minimized by adding additional capacitor elements in series with the gate electrode, which itself functions as a capacitor. The input capacitance of a transmission line is reduced when capacitors are added in series according to:
1/C.sub.gate=.sub.lj(1/C.sub.FET.+1/C.sub.SERIES CAPj)(3)

(28) However, limited instantaneous bandwidth is a drawback of series capacitors, so it is desirable to add additional series capacitance elements to the gate electrode to reduce the gate's input capacitance and improve gate switching speeds.

(29) A further aspect of the invention is to arrange the passive components, preferably tight tolerance passive components, in such a way as to cause the gate electrode to function as a critically dampened transmission line that is resonant at the desired switching speed(s) .sub.switch. The low loss, tight component tolerances enabled by LCD manufacturing methods allow high-Q transmission line structures to be constructed. When power management control topology uses time-based switching modes, it is preferable to tune the resonant gate electrode to have a narrow pass band. However, when control topologies utilize frequency-based switching modes, it is preferable to tune the resonant gate electrode to have a bandwidth that overlaps the frequencies of interest to the control topology.

(30) As mentioned above, transmission lines and circuits consisting of a plurality of series capacitors will have reduced capacitance at the expense of narrower instantaneous bandwidth. Therefore, it is desirable to introduce inductor elements 35,71 within the resonant gate transistors 11,59 that cause the gate signal to have broader instantaneous bandwidth and to be resonant at the desired switching frequencies .sub.switch pre-determined by the inductance of the inductor elements 35,71 and the total capacitance of the gate structure segment 19,72 and embedded capacitors 33,67,69 as defined by equation 3.

(31) Reference is now made to FIGS. 4A,4B to illustrate resonant circuit tuning by means of embedding passive components within the transistor's resonant gate. FIG. 4A illustrates a resonant RLC circuit constructed by embedding the passive components in series. A resonant series RLC circuit 170 consists of a voltage source 171 that drives a current 172 through a resistive element 174 (R), an inductive element 176 (L), and a capacitive element 178 (C) configured in series connection. The order of the embedded passive elements 174,176,178 may vary in their sequence, and, in fact may contain a plurality of elements, such as a plurality of active series capacitors 100 and embedded series capacitors 110 in sequence with one another to reduce the gate's input capacitance in accordance with equation 3. Similarly, the passive elements 174,176,178 may be embedded in series to form a resonant series RLC circuit 170 that forms a resonant transmission line segment (42A,42B,42C,42D) so that a plurality of resonant transmission line segments are, in turn, connected in series to form a resonant transistor gate 11,59 as depicted in FIGS. 1C&1D.

(32) Resonant RLC circuits may also be constructed by embedding the passive circuit components in parallel as depicted in FIG. 4B. A resonant parallel RLC circuit 180 consists of a voltage source 181 that drives a current 182 through a resistive element 184 (R), an inductive element 186 (L), and a capacitive element 188 (C) configured in parallel connection. Parallel circuits may also contain a terminating resistor 190 (R). The order of the embedded passive elements 184,186,188 may vary in their sequence, and, in fact may contain a plurality of elements, such as a plurality of active series capacitors 100 and embedded parallel capacitors 120 in sequence with one another to tune the gate's capacitance. Similarly, the passive elements 184,186,188 may be embedded in parallel to form a resonant series RLC circuit 180 that actually forms a resonant transmission line segment so that a plurality of resonant transmission line segments are, in turn, connected in series to form a resonant transistor gate 11,59.

(33) Transmission lines and circuits that contain inductors and capacitors, in series or in parallel, will display resonant characteristics. While it is advantageous for the resultant transmission line to be resonant at the switching frequency, .sub.switch1, resonance can cause deleterious effects when not properly damped. The characteristic solution of an RLC circuit is expressed in terms of its natural resonant frequency, .sub.o, and damping factor, , is:
x=Ae.sup.st(4a) where,
s=(.sup.2.sub.o.sup.2)(4b) and the circuit's natural frequency .sub.o is determined by
.sub.o=2.sub.o=1/(LC)(4c) x applies to the gate voltage when a series RLC circuit is considered and applies to the source current in the case of a parallel RLC circuit. Resistive elements, which include the conductive electrode element in the active and passive components, act as dampening force on the circuit. In parallel RLC circuits the damping coefficient is given by:
=1/(2R(C/L)),(4d) and in series RLC circuits the damping coefficient is given by:
=R/(2(L/C)).(4e)

(34) It is often desirable to tune the resonant gate transistors 11,59 to be critically damped at the switching frequency to minimize settling times. Over-dampening occurs in RLC circuits when >.sub.o and typically produces long settling times and large steady state errors. Under-dampening occurs when <.sub.o and are prone to signal ring, and have oscillations that decay over longer than desirable time periods. Critical dampening occurs when =.sub.o. Often the resistance of the conductive elements in the active and passive components forming the gate electrode is insufficient to achieve critical dampening. In these instances, it is desirable to introduce resistive elements 31,66 within the resonant gate transistors 11,59.

(35) It is advisable to broaden the frequency bandwidth of the gate electrode when frequency-based control topologies are applied to manage power in these circuits. Bandwidth is proportional to the damping coefficient in LCR circuits and is given, in units of Hertz, by:
=/2=/=R/2L.(5)

(36) In many instances it is desirable design objective to broaden the bandwidth by adding extra resistance to the resonant gate transistor 11,59 using a terminal resistor 160 as shown in FIG. 3G. The terminal resistor 160 is affixed to the end terminal 162 of the innermost circumferential gate structure segment 71 in a resonant gate vertical FET 59, or is used to terminate a resonant gate surface FET 11. It consists of a resistive element 164 that may be a tight tolerance dielectric material or conductive material that is in electrical contact with ground (the source electrode). In the case of a resonant gate vertical FET, the resistive element 164 is in electrical communication with a terminating electrode 166 that has a portion 168 that protrudes from any insulating material (not shown) to allow the terminating electrode 166 to make electrical contact with the overlaying source electrode 63.

(37) The resonant gate transistors need not be constructed from simple series-only and parallel-only lumped circuits. These simple circuits allow for convenient expressions because they can be reduced to closed analytical formula. Numerical methods now provide means to determine resonant frequency response in more complex structures that contain a plurality of embedded passive components configured in series and parallel connections within a plurality of resonant transmission line segments as shown in FIG. 5C. Furthermore, at frequencies high enough for the physical structure of the resonant gate transistor 11,59 to have dimensions comparable to the gate signal's electromagnetic wavelength it may become necessary for individual resonant transmission line segments among a plurality of such segments to have varied tunings that account for transmission line delays and provide better impedance matching within the overall circuit.

(38) Reference is now made to FIGS. 5A-5F to illustrate an alternative resonant gate transistor that has the benefit of providing lower cost through simplified assembly techniques. This embodiment of the invention incorporates elements of copending applications de Rochemont '922 and '654. FIG. 5A depicts a perspective view of a monolithic power management module 200 formed on a semiconductor 202 that comprises a toroidal inductor coil 204, an embedded diode 206, a controller circuit 208, and an output capacitor 210. The monolithic power management module 200 is shown with its source electrode removed to reveal a dielectrically loaded serpentine resonant gate transistor 212. Although FIG. 5A depicts this embodiment applied to a vertical power FET, the principles outlined below can also be applied to a resonant gate surface using methods similar to those described above.

(39) A close up top view of FIG. 5A is provided in FIG. 5B. The dielectrically loaded serpentine resonant gate transistor 212 is modulated by a signal supplied through a gate feed 214 and has a primary termination 216 that may comprise a terminating resistor 160. The serpentine resonant gate transistor 212 may consist of a plurality of linear gate segments 218 and/or arcuate gate segments 220 that electromagnetically couple with one another to establish resonance at a desired frequency or band of frequencies. The primary gate segment 221, (shown here as an arcuate segment that circumferentially traverses the exterior of the dielectrically loaded serpentine resonant gate transistor 212), directly connects the gate feed 214 to the primary termination 216. The primary gate segment 221 may also contain one or more major branching points 222 that split off additional gate segments 224A,224B,224C,224D to extend the serpentine gate along a different path than the primary gate segment. Each additional gate segment 224A,224B,224C,224D may have one or more additional branching points 226B,226C that in turn split-off additional serpentine gate segments, which have secondary termination points 228A that may or may not include a terminating resistor 160. As described below, the electromagnetic coupling within the serpentine paths traversed within each additional gate segment 224A,224B,224C,224D establish the resonant characteristics of the transistor. These paths may form any imaginable path, including paths produced by the application of fractal geometries.

(40) FIG. 5C details a preferred method of electromagnetic coupling that relies upon current vector alignment. The arrows represent instantaneous current vectors 230 of the gate signal as it flows along the branched serpentine path. Inductive reactive loading is generated along the branched serpentine path where the instantaneous current vectors 230 have parallel vector alignment 232A,232C,232D with adjacent portions of the gate within the additional gate segment 224A. Parallel vector alignments 232B,232E may also be established along portions that comprise neighboring additional gate segments 224B,224C. Capacitive reactive loading is generated along the branched serpentine path where the instantaneous current vectors 230 have anti-parallel (opposing direction) vector alignment 234A,234B within the additional gate segment 224A. Anti-parallel vector alignments (not shown) may also be established along portions that comprise neighboring additional gate segments 224B,224C.

(41) The inductance generated by inductive coupling between two parallel wire segments in the absence of a ground plane can be given by:

(42) $\begin{array}{cc}{L}_{\mathrm{pair}}=\frac{{\mathrm{.Math.}}_o{\mathrm{.Math.}}_r}{}\left[\frac{d}{2r}+\sqrt{\frac{d^2}{4r^2}-1}\right]& \left(6\right)\end{array}$ where l is the coupling length, d is gap between the wires and r is the radius of the wire, all in meters, .sub.o is the free-space permeability, and .sub.r is the permeability of the material separating the parallel wires. Similarly, the capacitance generated by capacitive coupling between two parallel wire segments in the absence of a ground plane can be given by:
C=l.sub.o.sub.r ln(d/r)(7) where l is the coupling length, d is gap between the wires and r is the radius of the wire, all in meters, .sub.o is the permittivity of free-space, and .sub.r is the relative permittivity of the material separating the parallel wires.

(43) Equations 6&7 linearly correlate the strength of the reactive loading (inductive or capacitive) with the coupling length l. (the physical separation of electromagnetically coupled gate segments) and the dielectric density (.sub.r,.sub.r) of the material located between the co-linear portions of adjacent gate segments. Therefore, it is a distinct embodiment of the invention to use LCD methods to insert tight tolerance dielectric material with co-linear portions of adjacent gate segments to tune the resonant characteristics of the dielectrically loaded serpentine resonant gate transistor 212. LCD methods are used to tune the gate's resonant response by inserting high permeability dielectric loads 236, having .sub.r10, within the spacing between adjacent gate segments that exhibit parallel instantaneous current vector alignments 232A,232B,232C,232D,232D (where desired), and inserting high permittivity dielectric loads 238, having .sub.r10, with the spacing between adjacent gate segments that exhibit anti-parallel instantaneous current vector alignments 234A,234B (where desired).

(44) FIG. 5D depicts the RLC circuit diagram corresponding to the localized reactive loads generated by the parallel and anti-parallel current vector alignments introduced along the serpentine path for the additional gate segment 224A shown in FIG. 5C. FIG. 5D assumes terminating resistors 160 are used in all secondary termination points 228. FIG. 5E depicts the RLC circuit diagram for the dielectrically loaded serpentine gate transistor when all of the branched additional gate segments 224A,224B,224C,224D are configured in parallel electrical connection (as shown in FIG. 5B) and has its primary termination 216 terminated with a resistor.

(45) This technique allows a simple circuit layout to easily construct a fairly complex resonant RLC circuit. The complexity of the circuit shown in FIG. 5D requires numerical methods to determine the gate's resonant frequency response, however, this technique provides a simplified construction methods to construct complex circuit that provides greater control in precisely tuning a resonant transistor gate that operates at a desired frequency or range of frequencies. Greater tuning precision is achieved apportioning the dielectric load within coupled gate segments into a plurality of sub-segments 238A,238B,238C,238D,238E in which different materials having varying dielectric densities are inserted. The addition of the dielectric loads alters the construction of the FET. Segments of the dielectrically loaded serpentine resonant gate transistor 212 that are not dielectrically loaded may be constructed in accordance with FIGS. 1D,2C. The addition of dielectric loads displaces the placement of active junctions and overlaying source electrodes. FIG. 5F depicts the C-C cross-sectional view of a dielectrically loaded serpentine gate transistor 212 configured for operation as a FET. FIG. 5F adds the source electrode 240 not shown in FIGS. 5A-5C. When configured as a vertical FET the dielectrically loaded serpentine resonant gate transistor 212 uses the same semiconductor layered structure as a standard vertical FET. It consists of a drain electrode 242, a semiconductor drain layer 244, an intrinsic n-type semiconductor layer 246 that has p-doped regions 248 that form the active junction and n+-doped regions 250 that form an ohmic contact with the source electrodes 240. A voltage applied to the gate electrodes 252A,252B modulates conductive channels 254A,254B immediately beneath the gate oxide 256, which also insulates the gate electrodes 252A,252B from the source electrode 240. The dielectric load 258 is inserted between the parallel gate electrodes 252A,252B. The purpose of the dielectric load 258 is to enhance electromagnetic coupling between parallel gate electrodes 252A,252B, therefore the semiconductor material immediately beneath the dielectric load 258 is inactive. A barrier material (not shown) may be inserted between the dielectric load 258 and the intrinsic n-type semiconductor layer 246 to prevent the diffusion of elemental components of the dielectric load 258 into the semiconductor layers, if needed.

(46) A final embodiment of the present invention integrates monolithic power management modules comprising a resonant gate transistor using any of the methods outlined above onto a semiconductor chip carrier. FIG. 6 depicts a chip carrier 300 that electrically interconnects a plurality of semiconductor die 302A, 302B, 302C, 302D, 302A, 302B, 302C, 302D mounted on a semiconductor substrate 304. At least one monolithic power management module containing a power FET with a resonant gate transistor 306 is formed on the surface of the semiconductor substrate 304. Additional active and passive circuitry may also be embedded within or formed upon the semiconductor substrate 304. Since switching speeds are constrained by the electron mobility, which in silicon is .sub.elec=1,300 cm.sup.2V.sup.1sec.sup.1. It is therefore desirable to utilize semiconductors, such as silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs) or other III-V compound semiconductors, or when the application warrants, II-VI compound semiconductors, which have higher electron mobility than silicon (Si) within the monolithic power management module 306.

(47) The present invention is illustratively described above in reference to the disclosed embodiments. Various modifications and changes may be made to the disclosed embodiments by persons skilled in the art without departing from the scope of the present invention as defined in the appended claims.