INTEGRATED CIRCUIT PACKAGE

Abstract

An integrated circuit package includes a support substrate and a cover fastened on a first face of the support substrate. The cover and support substrate define a housing containing an electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements. A first space between the cover and a second face of the electronic integrated circuit chip is filled with a first shape memory material in the austenitic state. A second space between each pair of electrically conductive protruding elements and electrically conductive contact pads of the support substrate is filled with a second shape memory material in the austenitic state.

Claims

1. An integrated circuit package, comprising: a support substrate including a first face with electrically conductive contact pads; a cover fastened on a first face of the support substrate and defining, with the support substrate, a housing; at least one electronic integrated circuit chip contained within the housing; wherein the at least one electronic integrated circuit chip has a first face equipped with electrically conductive protruding elements and a second face opposite to the first face; wherein the electrically conductive protruding elements of the at least one electronic integrated circuit chip are in electrical cooperation with the electrically conductive contact pads of the support substrate via a first shape memory material that is electrically conductive.

2. The package according to claim 1, wherein the first shape memory material is thermally conductive.

3. The package according to claim 1, wherein a space between the first face of the at least one electronic integrated circuit chip and the first face of the support substrate is devoid of filler material.

4. The package according to claim 1, wherein a space between the first face of the at least one electronic integrated circuit chip and the first face of the support substrate is devoid of adhesive material.

5. The package according to claim 1, wherein the first shape memory material has a temperature of end of transition to an austenitic state comprised between 40 C. and 100 C.

6. The package according to claim 1, wherein the first shape memory material contains a nickel-titanium alloy.

7. The package according to claim 6, wherein the first shape memory material contains a first amount of non-porous nickel-titanium alloy and a second amount of porous nickel-titanium alloy.

8. The package according to claim 7, wherein the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy.

9. The package according to claim 7, wherein the porous nickel-titanium alloy has a modulus of elasticity comprised between 10 GPa and 100 GPa.

10. The package according to claim 6, wherein the first shape memory material contains copper in an amount which is less than or equal to 5% of a total amount of the first shape memory material.

11. The package according to claim 1, wherein the first shape memory material is positioned between a distal end of the electrically conductive protruding element and a surface of the electrically conductive contact pad.

12. The package according to claim 1, wherein a space between the second face of the at least one electronic integrated circuit chip and the cover is filled with a second shape memory material.

13. The package according to claim 12, wherein the second shape memory material is thermally conductive.

14. The package according to claim 13, wherein the first shape memory material and the second shape memory material are identical.

15. The package according to claim 12, wherein the first shape memory material and the second shape memory material each contain a nickel-titanium alloy.

16. The package according to claim 15, wherein the first shape memory material and the second shape memory material each contain a first amount of non-porous nickel-titanium alloy and a second amount of porous nickel-titanium alloy.

17. The package according to claim 16, wherein the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy.

18. The package according to claim 16, wherein the porous nickel-titanium alloy has a modulus of elasticity comprised between 10 GPa and 100 GPa.

19. The package according to claim 12, wherein the first shape memory material and the second shape memory material each also contain copper in an amount which is less than or equal to 5% of a total amount of the corresponding shape memory material.

20. A method for manufacturing an integrated circuit package, comprising: a) providing at least one electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements; b) providing a support substrate having a first face equipped with electrically conductive contact pads; c) flipping the at least one electronic integrated circuit chip and causing the protruding elements to electrically cooperate with the electrically conductive pads; d) providing a first layer of a first shape memory material in a martensitic state and having an initial thickness; e) deforming the first layer so as to give it a second thickness which is less than the initial thickness and depositing the first layer thus deformed on a second face of the at least one electronic integrated circuit chip which is opposite to the first face; f) fastening a cover on the first face of the support substrate so as to cover the first layer, leaving a space between the first layer and the cover; and g) heating the structure obtained in step f) to a temperature which is higher than a temperature of end of transition to an austenitic state of the first shape memory material so that the first layer expands in thickness to fill said space by ensuring a pressure on the cover.

21. The method according to claim 20, wherein the first shape memory material is thermally conductive.

22. The method according to claim 20, further comprising between step b) and step c) depositing, on the electrically conductive contact pads, a second layer of a second shape memory material that is electrically conductive and deformed in the martensitic state, and wherein step c) comprises flipping the at least one electronic integrated circuit chip and causing the protruding elements to electrically cooperate with the electrically conductive pads via the second layer of the second shape memory material, and wherein in step g) a thickness of the second layer of the second shape memory material increases so as to ensure a pressure on said protruding elements.

23. The method according to claim 22, wherein the second shape memory material is identical to the first shape memory material.

24. The method according to claim 20, wherein the first shape memory material contains a nickel-titanium alloy.

25. A method for manufacturing an integrated circuit package, comprising: a) providing at least one electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements; b) providing a support substrate having a first face equipped with electrically conductive contact pads; c) providing a first layer of a first shape memory material in a martensitic state and having an initial thickness; d) deforming the first layer so as to give it a second thickness which is less than the initial thickness and depositing the first layer thus deformed on the electrically conductive contact pads; e) flipping the at least one electronic integrated circuit chip and causing the protruding elements to electrically cooperate with the electrically conductive pads through the first layer; f) fastening a cover on the first face of the support substrate; g) heating the structure obtained in step f) to a temperature which is higher than a temperature of end of transition to an austenitic state of the first shape memory material so that the first layer expands in thickness to apply a pressure against on the electrically conductive protruding elements.

26. The method according to claim 25, wherein the first shape memory material contains a nickel-titanium alloy.

27. The method according to claim 25, further comprising: providing a second layer of a second shape memory material in a martensitic state and having an initial thickness; deforming the second layer so as to give it a second thickness which is less than the initial thickness and depositing the second layer thus deformed on a second face of the at least one electronic integrated circuit chip which is opposite to the first face; wherein step f) fastens the cover over the second layer, leaving a space between the second layer and the cover; and wherein the temperature of the heating in step g) is higher than a temperature of end of transition to an austenitic state of the second shape memory material so that the second layer expands in thickness to fill said space by ensuring a pressure on the cover.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other advantages and features of the invention will appear on examining the detailed description of embodiments and implementations, without limitation, and the appended drawings in which:

[0031] FIG. 1 shows a cross sectional view of an integrated circuit package;

[0032] FIG. 2 shows in more detail a part of the integrated circuit package of FIG. 1;

[0033] FIG. 3 shows in more detail a part of the integrated circuit package of FIG. 1; and

[0034] FIG. 4 shows steps in a method of manufacturing the integrated circuit package of FIG. 1.

DETAILED DESCRIPTION

[0035] In FIG. 1, the reference BT designates an integrated circuit package.

[0036] This package BT comprises a support substrate 1, of a structure which is conventional and known per se, including a first face F1, typically the upper face of the support substrate.

[0037] The lower face of the support substrate, opposite to the upper face F1, is generally provided with solder balls (not explicitly shown) intended to be soldered onto the tracks of a printed circuit board.

[0038] The package BT also includes a cover 2, also of a structure which is conventional and known per se.

[0039] This cover 2 is fastened on the first face F1 of the support by means, in particular, of an adhesive material 8 such as a glue.

[0040] The cover 2 defines, with the support substrate 1, a housing 3 containing at least one electronic integrated circuit chip 4.

[0041] The chip 4 includes a first face 41, typically the front face, equipped with electrically conductive protruding elements 5 such as bumps or pillars, for example made of copper.

[0042] The chip 4 also includes a second face 42, opposite to the first face 41, typically the rear face of the chip.

[0043] The chip 4 is mounted in a flip chip orientation, that is to say that the front face 41 faces the support substrate 1 while the rear face 42 faces the cover 2.

[0044] The rear face 42 of the chip 4 is located at a distance d1 from the cover 2 and defines therewith a first space ESP1 which is completely filled with a first shape memory material 7 shown in FIG. 1 in the austenitic state.

[0045] By way of non-limiting example, the first shape memory material 7 may contain a nickel-titanium alloy known to the person skilled in the art under the name Nitinol, in which titanium and nickel are approximately present in the same percentages.

[0046] The chemical formula of Nitinol is, for example, Ni.sub.14Ti.sub.11. However, shape memory materials having other compositions may also be referred to in practice by the term Nitinol.

[0047] A shape memory material is a material with a property which is well known to the person skilled in the art.

[0048] It is recalled that this shape memory property is defined as the ability of a sample of this material having undergone a significant deformation to recover its initial shape in the austenitic state by heating to a temperature which is higher than the temperature of end of transition to the austenitic state, a temperature known to the person skilled in the art under the expression austenite finish.

[0049] Thus, the temperature of end of transition to the austenitic state of Nitinol is in the range of 50 C. to 100 C.

[0050] Nitinol is a shape memory material which is both thermally and electrically conductive.

[0051] Its thermally conductive nature allows it to contribute to the heat dissipation of the package.

[0052] As very schematically illustrated in FIG. 1, the package BT includes electrically conductive contact pads 6, distributed over the first face F1 of the carrier substrate.

[0053] And, the protruding elements 5 are in seamless electrical cooperation with these contact pads 6.

[0054] More specifically, in the embodiment of FIG. 1, distal ends of the protruding elements 5 are in contact with a second shape memory material 9, which, in the present case, is identical to the first shape memory material 7. In other words, the second shape memory material 9 also contains Nitinol.

[0055] And, as Nitinol is electrically conductive, the protruding elements 5, in contact with the Nitinol layer 9 which covers the upper surface of the corresponding contact pad 6, are indeed in electrical cooperation with these contact pads 6.

[0056] And this electrical cooperation is performed seamlessly.

[0057] Furthermore, as illustrated in FIG. 1, the first face 41 of the chip 4 defines, with the first face F1 of the carrier substrate, a second space ESP2 devoid of filler material (underfill) or adhesive material such as a glue.

[0058] Now, reference is made more particularly to FIG. 2 which schematically illustrates a zoom of the zone ZA of FIG. 1.

[0059] As shown in FIG. 2, the layer 9 of shape memory material is trapped in an insulating enclosure 10, known to the person skilled in the art by the name Solder Mask.

[0060] The shape memory material 9 is herein also in its austenitic state and creates a spring effect exerting a thrust on the protruding element 5 in the direction of the arrow F2, in other words in the direction of the protruding elements 5.

[0061] In parallel, as schematically illustrated in FIG. 3, the shape memory material 7 located between the rear face 42 of the chip 4 and the cover 2 exerts a spring effect tending to push the chip 4 back in the direction of the arrow F1, in other words in the direction of the support substrate.

[0062] The combination of these two spring effects leads to a very good electrical contact between the distal end 50 of the protruding elements 5 and the layer 9 of the shape memory material and therefore a very good electrical cooperation between the protruding element 5 and the upper surface of the underlying corresponding contact pad 6, and this without the need to perform any soldering at the protruding elements.

[0063] Obtaining these spring effects will now be described with more particular reference to FIG. 4 which very schematically illustrates the steps of the method for manufacturing the package BT of FIG. 1.

[0064] In step STa, the electronic integrated circuit chip 4 is provided having the first face 41 thereof equipped with electrically conductive protruding elements 5.

[0065] In step STb, the support substrate 1 is provided having the first face F1 thereof equipped with electronically conductive contact pads 6.

[0066] Then, in step STc, the chip 4 is flipped to cause the protruding elements 5 to seamlessly electrically cooperate with the electrically conductive pads 6.

[0067] When it is also planned to use a shape memory material 9 on the side of the protruding elements, between step STb and step STc, is planned a step STb1 in which a layer of the shape memory material 9, which has been deformed in the martensitic state, is deposited in compression so as to have a height H2 which is less than the height H1 mentioned in FIG. 2.

[0068] And, in this case, in step STc, after flipping the chip, there is a seamless electrical cooperation of the protruding elements with the corresponding electrically conductive pads 6 via the layer of this shape memory material.

[0069] Then, in step STd, a first layer of the shape memory material 7 is provided having an initial thickness d0 which is greater than the distance d1 mentioned in FIG. 1.

[0070] Then, in step STe, this first layer is deformed in the martensitic state by compression, so as to give it a second thickness d2 which is less than the initial thickness d0, this second thickness d2 also being slightly less than the distance d1 mentioned in FIG. 1.

[0071] As an indication, for a given distance d1, a second thickness d2 will be selected, which is less than the distance d1, for example in the range of 1% to 5% less of the distance d1.

[0072] Then, the first layer thus deformed is deposited on the rear face 42 of the flip chip.

[0073] Then, in step STf, the cover 2 is fastened on the support substrate 1 via the glue 8 which is, for example, a pre-polymerized glue.

[0074] As the thickness of the shape memory material layer 7 is slightly less than the distance d1 between the rear face of the chip and the cover 2, a space thus remains between this layer 7 and the cover which allows its fastening on the support substrate while covering the chip.

[0075] Finally, the fastening of the cover on the support substrate is completed in step STg by heating the structure obtained in step STf to a temperature which is higher than the temperature of end of transition to the austenitic state of the shape memory material. This heating allows, on the one hand, completely polymerizing the glue 8 and, on the other hand, causing the shape memory material to pass into its austenitic state so that it regains its initial shape, in this case so that the material layer 7 increases in thickness to tend to regain its initial thickness which is greater than the distance d1.

[0076] As a result, the space ESP1 is completely filled by the shape memory material 7 and it ensures its spring effect as schematically illustrated in FIG. 3.

[0077] When the shape memory material layer 9 has also been deposited in the enclosure 10, the heating to the temperature which is higher than the temperature of end of transition to the austenitic state leads to an increase in the thickness of the layer 9 which causes the spring effect illustrated in FIG. 2.

[0078] As an indication, in step STG, the package will be heated to a temperature in the range of a hundred degrees, depending on the used materials.

[0079] The package according to these embodiments and implementations therefore uses a shape memory material, for example nitinol, acting as a spring allowing a proper electrical cooperation between the protruding elements 5 and the underlying contact pads of the support substrate, and this seamlessly, and even in the case of warping of the support substrate.

[0080] There is no soldering at the protruding elements 5 and consequently no stress transmitted to the chip.

[0081] There is no filler material in the structure and no stress appearing during the life of the product.

[0082] The invention is not limited to the implementations and embodiments which have just been described, but encompasses all variants thereof.

[0083] Thus, it is possible to use for the shape memory materials 7 and 9, non-porous Nitinol and porous Nitinol, which allows increasing the elongation capacity of the shape memory material.

[0084] It is also possible that the shape memory material also contains copper in an amount which is less than or equal to 5% of the total amount of the corresponding shape memory material.

[0085] Indeed, the presence of copper in small amounts allows reinforcing the bidirectional effect of the shape memory material.