Integrated Assemblies and Methods of Forming Integrated Assemblies

Abstract

Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

Claims

1. An integrated assembly, comprising: a stack of alternating first and second levels; a panel extending through the stack; and the first levels having proximal regions adjacent the panel, and having distal regions further from the panel than the proximal regions; the distal regions comprising conductive structures, with said conductive structures having a first thickness; the proximal regions comprising insulative structures, with said insulative structures having a second thickness at least about as large as the first thickness.

2. The integrated assembly of claim 1 wherein the panel separates a first memory-block-region from a second memory-block-region.

3. The integrated assembly of claim 1 comprising channel-material-pillars extending through the stack.

4. The integrated assembly of claim 1 wherein the second levels comprise void regions between the distal regions of the first levels.

5. The integrated assembly of claim 1 wherein the second thickness is larger than the first thickness.

6. The integrated assembly of claim 1 wherein the second thickness is at least about 10% larger than the first thickness.

7. The integrated assembly of claim 1 wherein the second thickness is at least about 20% larger than the first thickness.

8. The integrated assembly of claim 1 wherein the insulative structures are substantially rectangular-shaped along a cross-section.

9. The integrated assembly of claim 1 wherein the insulative structures comprise silicon and nitrogen.

10. The integrated assembly of claim 1 wherein the insulative structures comprise silicon nitride.

11. The integrated assembly of claim 1 wherein each of the conductive structures includes a tungsten-containing core and a metal-nitride-containing liner along an outer periphery of the tungsten-containing core.

12. The integrated assembly of claim 11 wherein the distal region of each of the first levels includes dielectric material along an outer periphery of the metal-nitride-containing liner.

13. The integrated assembly of claim 12 wherein the distal regions of the first levels have overall thicknesses which encompass the conductive structures and the dielectric material.

14. The integrated assembly of claim 13 wherein the second vertical widths of the insulative structures are at least about a large as the overall thicknesses of the distal regions.

15. The integrated assembly of claim 13 wherein the dielectric material is a high-k material.

16. An integrated assembly, comprising: a vertical stack of alternating void levels and non-void levels; channel-material-pillars extending vertically through the stack; a panel extending vertically through the stack and separating a first memory-block-region from a second memory-block-region; and the non-void levels having proximal regions adjacent the panel, and having distal regions further from the panel than the proximal regions; the distal regions comprising conductive structures, with said conductive structures having a first vertical width; the proximal regions comprising insulative structures, with said insulative structures having a second vertical width at least about as large as the first vertical width.

17. The integrated assembly of claim 16 wherein the second vertical width is larger than the first vertical width.

18. The integrated assembly of claim 16 wherein the insulative structures comprise silicon nitride.

19. The integrated assembly of claim 16 wherein each of the conductive structures includes a tungsten-containing core and a metal-nitride-containing liner along an outer periphery of the tungsten-containing core.

20. The integrated assembly of claim 19 wherein the distal region of each of the non-void levels includes dielectric material along an outer periphery of the metal-nitride-containing liner.

21. The integrated assembly of claim 19 wherein the distal regions of the non-void levels have overall vertical widths which encompass the conductive structures and the dielectric material.

22. The integrated assembly of claim 21 wherein the second vertical widths of the insulative structures are at least about a large as the overall vertical widths of the distal regions.

23. The integrated assembly of claim 21 wherein the dielectric material is a high-k material.

24. A method of forming an integrated assembly, comprising: forming a stack of alternating first levels and second levels; the first levels comprising first material and the second levels comprising second material; forming openings to extend through the stack; forming charge-storage material, tunneling material and channel material within the openings; forming a slit to extend through the stack; flowing etchant into the slit to remove the first material and leave first voids between the second levels; forming conductive structures within the first voids; the conductive structures having proximal ends adjacent the slit; recessing the proximal ends to form cavities adjacent the slit along the first levels; forming insulative structures within the cavities; the insulative structures being between the slit and the recessed proximal ends of the conductive structures; removing the second material to leave second voids between the conductive structures; and forming a panel within the slit.

25. The method of claim 24 wherein the forming of the insulative structures comprises: forming insulative material within the slit, the insulative material extending into the cavities and forming liners along sidewalls of the slit; and removing some of the insulative material from within the slit, while leaving the insulative material within the cavities as the insulative structures.

26. The method of claim 25 wherein the second voids are formed within a memory region of an integrated assembly; wherein the integrated assembly includes another region peripheral to the memory region; wherein the stack extends across the memory region and said other region; and wherein the insulative material is formed to extend across said other region during the formation of the liners, and remains over said other region during the formation of the second voids within the memory region.

27. The method of claim 26 wherein the insulative material remaining over said other region during the formation of the second voids within the memory region precludes removal of the second material from within said other region.

28. The method of claim 24 wherein the panel separates a first memory-block-region from a second memory-block-region.

29. The method of claim 24 wherein the cavities are formed to be vertically wider than the conductive structures.

30. The method of claim 29 wherein the forming of the cavities comprises: forming first regions of the cavities by the recessing of the proximal ends of the conductive structures, exposed portions of the second material being adjacent said first regions, the first regions having an initial vertical width; and recessing the exposed portions of the second material to vertically widen the cavities beyond the initial vertical width.

31. The method of claim 24 wherein the insulative structures comprise silicon nitride.

32. The method of claim 24 wherein the first material comprises silicon nitride and the second material comprises silicon dioxide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

[0016] FIG. 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

[0017] FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in an X-X′ direction.

[0018] FIG. 4 is a schematic diagram of a prior art NAND memory array.

[0019] FIG. 5 is a diagrammatic top-down view of regions of an integrated assembly.

[0020] FIGS. 6 and 7 are diagrammatic cross-sectional side views of a region of an integrated assembly shown at example sequential process stages of an example method for forming an example NAND memory array.

[0021] FIG. 7A is a diagrammatic top-down view of a portion of the integrated assembly of FIG. 7. The view of FIG. 7 is along the line B-B of FIG. 7A, and the view of FIG. 7A is along the line A-A of FIG. 7.

[0022] FIG. 8 is a diagrammatic cross-sectional side view of the region of the integrated assembly of FIG. 6 shown at an example process stage following that of FIG. 7.

[0023] FIG. 8A is a diagrammatic top-down view of a portion of the integrated assembly of FIG. 8. The view of FIG. 8 is along the line B-B of FIG. 8A, and the view of FIG. 8A is along the line A-A of FIG. 8.

[0024] FIGS. 9-12 are diagrammatic cross-sectional side views of the region of the integrated assembly of FIG. 6 shown at example sequential process stages following that of FIG. 8.

[0025] FIG. 12A is a diagrammatic top-down view of a portion of an integrated assembly at the process stage of FIG. 12.

[0026] FIGS. 13-15 are diagrammatic cross-sectional side views of the region of the integrated assembly of FIG. 6 shown at example sequential process stages following that of FIG. 12.

[0027] FIG. 15A is a diagrammatic top-down view of a portion of the integrated assembly of FIG. 15. The view of FIG. 15 is along the line B-B of FIG. 15A, and the view of FIG. 15A is along the line A-A of FIG. 15.

[0028] FIGS. 16-18 are diagrammatic cross-sectional side views of the region of the integrated assembly of FIG. 6 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of FIG. 16 may follow that of FIG. 10.

[0029] FIG. 18A is a diagrammatic top-down view of a portion of the integrated assembly of FIG. 18. The view of FIG. 18 is along the line B-B of FIG. 18A, and the view of FIG. 18A is along the line A-A of FIG. 18.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0030] It can be desired to have voids between conductive structures to reduce, or even eliminate, capacitive coupling and/or other cross-talk mechanisms between the conductive structures. Some embodiments include integrated assemblies having voids between conductive structures. Some embodiments include methods of forming integrated assemblies. Example embodiments are described with reference to FIGS. 5-18.

[0031] FIG. 5 shows an integrated assembly 10 comprising a memory array region 100, and another region (peripheral region) 102 adjacent to the memory array region. The assembly 10 may be configured to include memory cells (e.g., NAND memory cells) across the memory array region 100. The memory cells may be addressed utilizing bitlines, wordlines, etc. The assembly 10 may include connections to the bitlines, wordlines, etc., within the peripheral region 102. For instance, a staircase region (which may also be referred to as a stadium region) may be provided within the peripheral region 102 and utilized for providing connections which couple the wordlines with appropriate driver circuitry.

[0032] Referring to FIG. 6, the memory array region 100 of the integrated assembly (integrated structure, construction) 10 is shown at an example process stage during the fabrication of memory cells. The assembly 10 includes a vertical stack 12 of alternating first and second levels 14 and 16. The first levels 14 comprise a first material 60, and the second levels 16 comprise a second material 62. The first and second materials may comprise any suitable compositions, and are of different compositions relative to one another. In some embodiments, the first material 60 may comprise, consist essentially of, or consist of silicon nitride; and the second material 62 may comprise, consist essentially of, or consist of silicon dioxide. The levels 14 and 16 may be of any suitable thicknesses; and may be the same thickness as one another, or may be different thicknesses relative to one another. In some embodiments, the levels 14 and 16 may have vertical thicknesses within a range of from about 10 nanometers (nm) to about 400 nm. In some embodiments, the levels 14 and 16 may have vertical thicknesses within a range of from about 10 nm to about 50 nm. In some embodiments, the first and second levels 14 and 16 may have vertical thicknesses within a range of from about 15 nm to about 40 nm, within a range of from about 15 nm to about 20 nm, etc. There may be any suitable number of levels 14 and 16 within the stack 12. In some embodiments, there may be more than 10 of the levels within the stack, more than 50 of the levels within the stack, more than 100 of the levels within the stack, etc.

[0033] The stack 12 is shown to be supported by (formed over) a source structure 17.

[0034] The source structure 17 may correspond to the source structures described with reference to FIGS. 1-4, and may be a line, an expanse, or any other suitable configuration. The source structure 17 may comprise any suitable materials, and in some applications may comprise conductively-doped semiconductor material (e.g., conductively-doped silicon) over metal-containing material (e.g., tungsten silicide).

[0035] The source structure 17 may be supported by a base (not shown). The base may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.

[0036] A gap is provided between the stack 12 and the source structure 17. The gap is utilized to indicate that other components and materials may be provided between the stack 12 and the source structure 17. Such other components and materials may comprise additional levels of the stack, source-side select gates (SGSs), etc. Similarly, a gap is provided over the stack to indicate that the stack may extend upwardly beyond the illustrated region of the stack, and to indicate that other components and materials (e.g., additional levels of the stack, bitlines, drain-side select gates (SGDs), etc.) may be provided over the illustrated region of the stack.

[0037] Referring to FIGS. 7 and 7A, openings 64 are formed to extend through the stack 12. The openings 64 may have any suitable shape along the top-down view of FIG. 7A, and may be circular (as shown), elliptical, square or other polygonal, etc.

[0038] The openings 64 may be representative of a large number of substantially identical openings formed at the process stage of FIGS. 7 and 7A. The term “substantially identical” means identical to within reasonable tolerances of fabrication and measurement.

[0039] Cell materials (memory cell materials) 34, 36, 42 and 44 are formed within the openings 64.

[0040] The cell material 34 is charge-blocking material. The charge-blocking material 34 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or both of silicon oxynitride (SiON) and silicon dioxide (SiO.sub.2).

[0041] The material 36 is charge-storage material. The charge-storage material 36 may comprise any suitable composition(s). In some embodiments the charge-storage material 36 may comprise one or more charge-trapping materials, such as, for example, one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc. For instance, in some embodiments the charge-storage material 36 may comprise, consist essentially of, or consist of silicon nitride.

[0042] The material 42 is gate-dielectric material (i.e., tunneling material, charge-passage material). The gate-dielectric material 42 may comprise any suitable composition(s). In some embodiments, the gate-dielectric material 42 may comprise, for example, one or more of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. The gate-dielectric material 42 may be bandgap-engineered to achieve desired electrical properties, and accordingly may comprise a combination of two or more different materials.

[0043] The material 44 is channel material. The channel material 44 comprises semiconductor material, and may comprise any suitable composition or combination of compositions. For instance, the channel material 44 may comprise one or more of silicon, germanium, III/V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups 13 and 15). In some embodiments, the channel material 44 may comprise, consist essentially of, or consist of silicon.

[0044] In the illustrated embodiment, insulative material 46 is formed adjacent the channel material 44, and fills central regions of the openings 64. The insulative material 46 may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. The illustrated embodiment of FIGS. 7 and 7A, shows the channel material 44 configured as an annular ring which surrounds the insulative material 46. Such configuration of the channel material may be considered to comprise a hollow channel configuration, in that the insulative material 46 is provided within a “hollow” in the annular-ring-shaped channel configuration. In other embodiments (not shown), the channel material may be configured as a solid pillar configuration.

[0045] The channel material 44 is shown to be electrically coupled with the source structure 17 in the cross-sectional view of FIG. 7. Such electrical coupling may be accomplished with any suitable configuration. For instance, in some embodiments the channel material 44 may directly contact the source structure 17.

[0046] The materials 34, 36, 42, 44 and 46 may have any suitable lateral thicknesses relative to one another. The illustrated embodiment is for diagrammatic purposes only. In other embodiments, the relative thicknesses of various of the materials 34, 36, 42, 44 and 46 may be different than shown in the illustrated embodiment of FIGS. 7 and 7A.

[0047] The materials 34, 36, 42 and 44 may be considered to be configured as cell-material-pillars 18 which extend vertically through the stack 12. In the shown embodiment, the cell-material-pillars 18 also include the insulative material 46.

[0048] The channel material 44 may be considered to be configured as channel-material-pillars 20 which extend vertically through the stack 12, with such channel-material-pillars being incorporated into the cell-material-pillars 18.

[0049] The illustrated cell-material-pillars 18 may be considered to be representative of a large number of substantially identical cell-material-pillars 18 that may be formed at the processing stage of FIGS. 7 and 7A. For instance, in some embodiments there may be hundreds, thousands, hundreds of thousands, millions, hundreds of millions, etc., of the cell-material-pillars formed at the processing stage of FIGS. 7 and 7A.

[0050] Referring to FIGS. 8 and 8A, a slit 66 is formed to extend through the stack 12. The slit 66 may be utilized to separate memory block regions from one another in some embodiments. The illustrated slit 66 may be representative of a large number of substantially identical slits formed at the process stage of FIGS. 8 and 8A.

[0051] Referring to FIG. 9, the first material 60 (FIG. 8) is removed, which leaves voids 30 along the first levels 14 (i.e., between the second levels 16), and subsequently the voids 30 are filled with conductive material 48 and dielectric material 28.

[0052] The voids 30 may be referred to as first voids, and may be formed with any suitable process which removes the material 60 (FIG. 8) selectively relative to the materials 62 and 34. In some embodiments such process may utilize etchant (e.g., hot phosphoric acid) flowed into the slit 66.

[0053] The dielectric material 28 may be high-k dielectric material, and may be referred to as dielectric-barrier material. The term “high-k” means a dielectric constant greater than that of silicon dioxide (i.e., greater than about 3.9). In some embodiments, the high-k dielectric material 28 may comprise, consist essentially of, or consist of one or more of aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicate (HfSiO), zirconium oxide (ZrO) and zirconium silicate (ZrSiO); where the chemical formulas indicate primary constituents rather than specific stoichiometries. The high-k dielectric material 28 may be formed to any suitable thickness; and in some embodiments may be formed to a thickness within a range of from about 1 nm to about 5 nm.

[0054] The conductive material 48 may comprise a single homogeneous composition, or may comprise a laminate of two or more different compositions. In the illustrated embodiment, dashed lines are provided within the conductive material 48 to indicate that the material 48 may comprise a conductive core material 52, and a liner material 54 along an outer periphery of the core material.

[0055] The conductive core material 52 may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive core material 52 may comprise one or more metals (e.g., may comprise tungsten).

[0056] The conductive liner material 54 may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, conductive liner material 54 may comprise one or more metal nitrides (e.g., may comprise titanium nitride, tungsten nitride, etc.).

[0057] In some embodiments, the dielectric-barrier material 28 may be considered to be along an outer periphery of the conductive liner material 54.

[0058] In some embodiments, the stack 12 of FIG. 9 may be considered to comprise alternating first and second levels 14 and 16, with the first levels 14 including the conductive material 48 and the dielectric-barrier material 28. The conductive material 48 may be considered to be configured as conductive structures 22 along the first levels 14. Some of the conductive structures 22 are adjacent to the slit 66. Such structures may be considered to have proximal ends 23 along the slit 66, and to have distal ends 25 in opposing relation to the proximal ends 23.

[0059] Referring to FIG. 10, the proximal ends 23 are recessed to form cavities 50 adjacent the slit 66 along the first levels 14. The cavities may have any suitable lateral depth D, including, for example, a lateral depth within a range of from about 10 nm to about 20 nm.

[0060] Referring to FIG. 11, insulative material 68 is formed over the assembly 10 and within the slit 66. In the illustrated embodiment, the insulative material partially fills the slit to form liners 70 along vertical sidewalls of the slit. The insulative material 68 also extends into the cavities 50 and fills such cavities.

[0061] The insulative material 68 may comprise any suitable composition(s), and in some embodiments may comprise a composition which includes silicon and nitrogen. For instance, the insulative material 68 may comprise, consist essentially of, or consist of silicon nitride.

[0062] Referring to FIG. 12, the liners 70 are thinned. FIG. 12A shows a top view of the assembly 10 at the process stage of FIG. 12. The assembly comprises the memory array region 100 and the peripheral region 102. A pair of the slits 66 are shown to pass through the illustrated portion of the memory array region 100. Staircase regions 104 are diagrammatically illustrated within the peripheral region 102. The insulative material 68 extends across the memory array region 100 and the peripheral region 102, and is shown to extend into the staircase regions 104.

[0063] Referring to FIG. 13, a portion of the insulative material 68 is removed so that the insulative material is no longer over the upper surface of the memory array region 100. Some of the insulative material is removed from within the slit 66, while leaving a remaining portion of the insulative material 68 within the cavities 50 as insulative structures 72. The insulative structures 72 are provided between the slit 66 and the recessed proximal ends 23 of the conductive structures 22.

[0064] In the illustrated embodiment, the conductive structures 22 have first thicknesses (vertical dimensions) T.sub.1, and the insulative structures 68 have second vertical thicknesses (vertical dimensions) T.sub.2. The second vertical dimensions T.sub.2 may be at least about as large as the first vertical dimensions T.sub.1. In some embodiments, the dielectric-barrier material 28 may be omitted from the levels 14, and in such embodiments the insulative structures 72 would have the same vertical dimensions as the conductive structures 22 in the illustrated configuration of FIG. 13. However, in the shown embodiment the dielectric-barrier material 28 is provided within the levels 14, and such levels may be considered to have overall thicknesses T.sub.3 which encompass the conductive structures 22 and the dielectric material 28. The thickness T.sub.2 of the insulative structures 72 may be at least about as large as the overall thickness T.sub.3.

[0065] The insulative structures 72 may have any suitable shapes, and in the illustrated embodiment are rectangular-shaped along the cross-sectional view of FIG. 13.

[0066] Referring to FIG. 14, the second material 62 (FIG. 13) is removed to leave voids 74 along the levels 16. The voids 74 may be considered to be between vertically-neighboring conductive structures 22, and between vertically-neighboring insulative structures 72. For instance, in the illustrated embodiment a pair of vertically-neighboring conductive structures 22 are labeled as 22a and 22b, and one of the voids 74 is labeled as 74a and is shown to be provided between (i.e., to be formed between) such vertically-neighboring conductive structures. Also, a pair of vertically-neighboring insulative structures 72 are labeled as 72a and 72b, and the void 74a is shown to be provided between such vertically-neighboring insulative structures.

[0067] The voids 74 may be referred to as second voids to distinguish them from the first voids 30 described above with reference to FIG. 9.

[0068] In some embodiments, the second voids 74 may be formed by flowing one or more suitable etchants into the slit 66.

[0069] The insulative material 68 may remain over the peripheral region 102 of FIG. 12A during the processing of FIGS. 13 and 14, and may protect the material 60 within such peripheral region from being removed during the processing of FIG. 14.

[0070] Referring to FIGS. 15 and 15A, a panel 76 is formed within the slit 66. The panel comprises panel material 78. The panel material 78 may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. Although the panel 76 is shown to comprise a single homogeneous material, in other embodiments the panel may comprise a laminate of two or more different materials.

[0071] The panel 76 may divide the pillars 18 between a first block region 106 and a second block region 108. Each of the pillars 18 may be considered to be associated with a vertical stack of memory cells (e.g., NAND memory cells) 110. Accordingly, the memory cells 110 on one side of the panel 76 may be considered to be within the first block region (memory-block-region) 106, and the memory cells 110 on the other side of the panel 76 may be considered to be within the second block region (memory-block-region) 108. The block regions 106 and 108 may be analogous to the memory blocks (or memory sub-blocks) described above in the “Background” section of this disclosure.

[0072] In some embodiments, the stack 12 of FIG. 15 may be considered to include alternating first and second levels 14 and 16, or alternatively to comprise void levels 16 alternating with non-void levels 14. The non-void levels (first levels) 14 may be considered to have proximal regions 80 adjacent the panel 76, and to have distal regions 82 further from the panel 76 than the proximal regions. The distal regions 82 comprise the conductive structures 22, and the proximal regions 80 comprise the insulative structures 72.

[0073] In the illustrated embodiment, the panel material 78 extends partially into the voids 74, and extends between vertically-neighboring insulative structures 72. However, the panel material does not extend far enough into the voids 74 to be between the vertically-neighboring conductive structures 22. In some embodiments, an advantage of the configuration of FIG. 15 is that the voids 74 extend a full length of the conductive structures 22, rather than having some portions of the conductive structures adjacent to insulative material 78 from the panel 76. Accordingly, the electrical separation between vertically-neighboring conductive structures remains consistent across the entirety of the conductive structures, rather than changing in regions neighboring to the panel 76 as can happen in conventional configurations lacking the insulative structures 72 between the conductive structures 22 and the panel 76. In some aspects, the airgap volume (void volume) between vertically-neighboring conductive structures 22 may be larger in configurations formed in accordance with embodiments described herein as compared to conventional configurations lacking the insulative structures 72 due to, at least in part, the lack of encroachment of the panel material 78 into regions directly between the conductive structures 22. The improved void volume may lead to improved electrical performance of vertically-adjacent wordlines (with the wordlines being the conductive structures 22) due to, at least in part, reduced crosstalk between the vertically-adjacent wordlines as compared to conventional configurations. Another advantage which may be achieved by utilizing the insulative structures 72 between the conductive structures 22 and the panel 76 is that there may be additional uniformity achieved relative to all of conductive structures 22 extending from the bottom of the panel 76 to the top of the panel 76 relative to configurations lacking the insulative structures 72. Such uniformity may include, for example, the extent to which the panel material 78 penetrates into the voids 74, and the associated consistency of seals provided by the panel 76 along the void regions 16. Further, the insulative structures 72 may provide improved adhesion between the panel material 78 and the non-void levels 14 as compared to conventional configurations lacking the insulative structures. Such may reduce cracking, bending and other problematic structural problems that may occur along interfaces of the panel 76 and the non-void levels 14 as compared to conventional configurations.

[0074] The non-void levels 14 may be considered to be memory cell levels (also referred to herein as wordline levels) of a NAND configuration. The NAND configuration includes strings of memory cells (i.e., NAND strings), with the number of memory cells in the strings being determined by the number of vertically-stacked levels 14. The NAND strings may comprise any suitable number of memory cell levels. For instance, the NAND strings may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0075] The NAND memory cells 110 comprise the dielectric-barrier material 28, the charge-blocking material 34, the charge-storage material 36, the gate-dielectric material 42 and the channel material 44. The illustrated NAND memory cells 110 form vertically-extending strings of memory cells. Such strings may be representative of a large number of substantially identical NAND strings formed during fabrication of a NAND memory array (with the term “substantially identical” meaning identical to within reasonable tolerances of fabrication and measurement).

[0076] Each of the NAND memory cells 110 includes a control gate region 90 within a conductive structure 22. The control gate regions 90 comprise control gates analogous to those described above with reference to FIGS. 1-4. The conductive structures 22 also comprise regions 92 adjacent to (proximate) the control gate regions 90. The regions 92 may be referred to as routing regions (wordline regions).

[0077] In operation, the charge-storage material 36 may be configured to store information in the memory cells 110. The value (with the term “value” representing one bit or multiple bits) of information stored in an individual memory cell may be based on the amount of charge (e.g., the number of electrons) stored in a charge-storage region of the memory cell. The amount of charge within an individual charge-storage region may be controlled (e.g., increased or decreased), at least in part, based on the value of voltage applied to an associated gate 90, and/or based on the value of voltage applied to the channel material 44.

[0078] The tunneling material 42 forms tunneling regions of the memory cells 110. Such tunneling regions may be configured to allow desired migration (e.g., transportation) of charge (e.g., electrons) between the charge-storage material 36 and the channel material 44. The tunneling regions may be configured (i.e., engineered) to achieve a selected criterion, such as, for example, but not limited to, an equivalent oxide thickness (EOT). The EOT quantifies the electrical properties of the tunneling regions (e.g., capacitance) in terms of a representative physical thickness. For example, EOT may be defined as the thickness of a theoretical silicon dioxide layer that would be required to have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations.

[0079] The charge-blocking material 34 may provide a mechanism to block charge from flowing from the charge-storage material 36 to the associated gates 90.

[0080] The dielectric-barrier material (high-k material) 28 may be utilized to inhibit back-tunneling of charge carriers from the gates 90 toward the charge-storage material 36. In some embodiments, the dielectric-barrier material 28 may be considered to form dielectric-barrier regions within the memory cells 110.

[0081] Some embodiments may include additional processing to form the insulative structures 72 to be substantially thicker (vertically wider) than the conductive structures 22. For instance, FIG. 16 shows a process stage which may follow that of FIG. 10. First regions of the cavities 50 may be considered to be formed at the process stage of FIG. 10. Portions of the second material 62 are exposed along such first regions at the process stage of FIG. 10. The first regions have an initial vertical width W.sub.1 at the process stage of FIG. 10. The exposed portions of the second material 62 are vertically recessed to extend the vertical width to a width W.sub.2 at the process stage of FIG. 16, which vertically widens the cavities 50.

[0082] FIG. 17 shows a process stage analogous to that of FIG. 14, but following the process stage of FIG. 16. Accordingly, the insulative structures 72 are formed, with such insulative structures comprising the insulative material 68. The insulative structures 72 have the second vertical thickness T.sub.2, and the conductive structures 22 have the first vertical thickness T.sub.1. In the configuration of FIG. 17, the second vertical thickness T.sub.2 is much larger than the first vertical thickness T.sub.1. In some embodiments, the vertical thicknesses of the insulative structures 72 may be at least about 10% larger than the vertical thicknesses of the conductive structures 22, at least about 20% larger than the vertical thicknesses of the conductive structures 22, etc. The voids 74 may extend between vertically-neighboring insulative structures 72 (as shown) or the neighboring insulative structures may merge with one another to form a continuous region of the insulative material 68 adjacent the slit 66.

[0083] FIGS. 18 and 18A show the configuration of FIG. 17 at a process stage analogous to that of FIG. 15. The configuration of FIGS. 18 and 18A includes the panel 76 formed within the slit 66. The panel 76 may separate the first memory-block-region 106 from the second memory-block-region 108.

[0084] The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0085] Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0086] The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

[0087] The terms “electrically connected” and “electrically coupled” may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow.

[0088] The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

[0089] The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

[0090] When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0091] Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

[0092] Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness.

[0093] Some embodiments include an integrated assembly having a vertical stack of alternating void levels and non-void levels. Channel-material-pillars extend through the stack. A panel extends through the stack and separates a first memory-block-region from a second memory-block-region. The non-void levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions comprise conductive structures, with said conductive structures having a first vertical width. The proximal regions comprise insulative structures, with said insulative structures having a second vertical width at least about as large as the first vertical width.

[0094] Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second levels is formed. The first levels comprise first material and the second levels comprise second material. Openings are formed to extend through the stack. Charge-storage material, tunneling material and channel material are formed within the openings. A slit is formed to extend through the stack. Etchant is flowed into the slit to remove the first material and to leave first voids between the second levels. Conductive structures are formed within the first voids. The conductive structures have proximal ends adjacent the slit. The proximal ends are recessed to form cavities adjacent the slit along the first levels. Insulative structures are formed within the cavities. The insulative structures are between the slit and the recessed proximal ends of the conductive structures. The second material is removed to leave second voids between the conductive structures. A panel is formed within the slit.

[0095] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.