HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING

Abstract

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

Claims

1. A semiconductor package comprising: a semiconductor die comprising a first side and a second side; a first trench comprised in the first side of the semiconductor die, the trench positioned outside an active area of the die; a lid comprising a second trench, the lid fixedly coupled to a first side of the semiconductor die by an adhesive; wherein the adhesive is comprised in the first trench in the first side of the semiconductor die and simultaneously comprised in the second trench positioned around a perimeter of the glass lid.

2. The semiconductor package of claim 1, wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof.

3. The semiconductor package of claim 2, wherein the adhesive is cured.

4. The semiconductor package of claim 1, wherein the adhesive is evenly distributed within the first trench and the second trench.

5. The semiconductor package of claim 1, wherein the adhesive extends out from the first trench and the second trench to further bond the lid and the semiconductor die.

6. The semiconductor package of claim 1, further comprising a redistribution layer coupled to the second side of the semiconductor die.

7. The semiconductor package of claim 5, further comprising a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer coupled to the semiconductor die.

8. A semiconductor package comprising: a semiconductor die comprising a first side and a second side; a first trench comprised around the perimeter of the first side of the semiconductor die; and a lid fixedly coupled to a first side of the semiconductor die by an adhesive, the adhesive comprised in a second trench around a perimeter of the lid; wherein the adhesive is simultaneously comprised in the first trench and the second trench, the trenches comprising corresponding locations in the semiconductor die and the lid.

9. The semiconductor package of claim 8, wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof.

11. The semiconductor package of claim 9, wherein the adhesive is cured.

12. The semiconductor package of claim 8, wherein the adhesive is evenly distributed within the first trench and the second trench.

13. The semiconductor package of claim 8, wherein the adhesive extends out from the first trench and the second trench to further bond the lid and the semiconductor die.

14. The semiconductor package of claim 8, further comprising: a redistribution layer coupled to a second side of the semiconductor die; and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer coupled to the semiconductor die.

15. A semiconductor package comprising: a semiconductor die comprising a first side and a second side; a first trench comprised around the perimeter of the first side of the semiconductor die; and one of a transparent or a translucent lid coupled to a first side of the semiconductor die by an adhesive, the adhesive comprised in a second trench around a perimeter of the lid; wherein the adhesive is simultaneously comprised in the first trench and the second trench, the trenches comprising corresponding locations in the semiconductor die and the one of the transparent or the translucent lid.

16. The semiconductor package of claim 15, wherein the adhesive is evenly distributed within the first trench and the second trench.

17. The semiconductor package of claim 15, wherein the adhesive extends out from the first trench and the second trench to further bond the lid and the semiconductor die.

18. The semiconductor package of claim 15, further comprising: a redistribution layer coupled to a second side of the semiconductor die; and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer coupled to the semiconductor die.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:

[0023] FIG. 1 is a side view of a conventional chip scale package;

[0024] FIG. 2 is a side view of a conventional through silicon via package;

[0025] FIG. 3 is a side view of a conventional chip scale package with a solder mask;

[0026] FIG. 4 is a side view of an implementation of a semiconductor package formed using adhesive in a trench around the perimeter of the semiconductor;

[0027] FIG. 5A-5E shows various processing steps involved in an implementation of a method for making a semiconductor package.

DESCRIPTION

[0028] This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended semiconductor package and method for making a semiconductor package will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such semiconductor packages, and implementing components and methods, consistent with the intended operation and methods.

[0029] FIG. 1 illustrates an implementation of a conventional chip scale package (CSP) 2. In this implementation, the CSP 2 is formed by coupling the glass lid 4 to the die 6 with an adhesive 8. In this example the adhesive is an ultraviolet (UV) curable resin 8. A solder mask 10 is then coupled/applied to the die to protect the die from environmental stress and eliminate the risk of delamination. The solder mask 10 and UV resin 8 are cured through the glass lid after the glass lid and die have been coupled together. In this implementation, there has been observed to be a high rate of delamination where the glass lid 4 separates from the die 6, as the semiconductor package 2 is exposed to electrical current. Referring to FIG. 2, an implementation of a conventional through silicon via (TSV) package 12 is illustrated. Here, the glass lid 14 and die 16 are covered with a dry film solder mask 18. The through silicon vias 20 that are connected to the redistribution layer 22 are also illustrated.

[0030] Referring to FIG. 3, a conventional CSP with solder mask moisture barrier is illustrated 24. This represents an improvement over the traditional CSP (FIG. 1) because the solder mask 26 covers the edge of the package 28 and die 30, where the glass lid and die meet, prior to singulation. This extra overlap helps to create a moisture barrier. However, to be implemented conventionally, this method needs the symmetrical design of aluminum pads at the four sides of the package and needs wide scribe line spaces for tapper structures at the package edge which decreases the gross die per wafer (GDPW) possible.

[0031] Referring to FIG. 4, an implementation of a semiconductor package 32 using a trench 34 is illustrated. The semiconductor die 36 is fixedly coupled on the first side to a glass lid 38 by an adhesive. The adhesive used may be, by non-limiting example, thermal curable resin, epoxy, ultraviolet light curable resin any combination thereof, or any other material capable of bonding the die to the glass lid. A redistribution layer 36 is coupled to a second side of the semiconductor die 32. The redistribution layer serves to route pads/balls on the semiconductor die to connectors that will be present on the circuit board to which the semiconductor package will ultimately be attached. A plurality of ball mounts 38 are coupled to the redistribution layer 36 on a side of the redistribution layer 36 opposing the side of the redistribution layer 36 coupled to the semiconductor die 32. The adhesive is located in/placed in a trench 34 around a perimeter of the semiconductor die 36 and is also located in/placed in a corresponding trench 34 around a perimeter of the glass lid 38. The adhesive present in the trench 34 formed from combined trenches in the glass lid 38 and the die 36 may form a hermetic seal and thereby prevents delamination. The increased strength of the bond between wafers may allow for chip stacking at any desired height of stacked chips.

[0032] Referring to FIGS. 5A-5E, a method for making a semiconductor package implementation is illustrated. In FIG. 5A, a glass wafer 42 and a semiconductor wafer 44 with active areas 46 are provided as illustrated. Referring to FIG. 5B, the formation of corresponding trenches 50 on the glass wafer 42 and semiconductor wafer 44 is illustrated. The trenches may be formed through one of stencil printing, sawing, lasering, wet etching, dry etching, any combination thereof or any other process that is capable of forming a trench-like structure in glass or semiconductor materials. Adhesive 48 may then be deposited into the corresponding trenches 46. The adhesive 48 may be any disclosed in this document. The adhesive 48 may be applied using, by non-limiting example, dispensing, spin coating, lithography, spray coating, stencil printing, spin etching, spray etching, any combination thereof, or any other process design to get the adhesive into the trench of the glass lid and/or semiconductor die. In some implementations, the method may include partially curing the adhesive 48 before coupling/bonding the glass wafer 42 to the semiconductor wafer 44.

[0033] In various implementations coupling/bonding of the glass wafer 42 and 44 may be accomplished by using, by non-limiting example, compression, heated compression, ultraviolet light exposure, curing, and combination thereof, or any other method of bonding two surfaces together. In some implementations, the surface energies of the exposed surfaces of the two wafers 42, 44 may be such that they bond when brought into contact with each other. During coupling/bonding of the glass wafer 42 and the semiconductor wafer 44, the trench of the semiconductor wafer 44 is aligned with the trench of the glass wafer 42. This may allow the adhesive present in the trenches to bond the semiconductor wafer 44 to the glass wafer 42, thereby forming one or more corresponding lids for the various one or more semiconductor die on the semiconductor wafer 44. In various implementations, all of the one or more semiconductor die may have the same size, or in others, one or more of the die may have different sizes/dimensions from other semiconductor die on the semiconductor wafer 44. In these implementations, the pattern of trenches in the glass wafer 42 may be altered to correspond with the pattern of trenches in the semiconductor wafer 44.

[0034] Referring to FIG. 5C, the effect of wafer bonding is illustrated wherein the glass wafer 42 and semiconductor wafer 44 are coupled together. In this implementation the adhesive 48 distributes evenly in the trenches 50 and between the wafers 42 and 44. In other implementations, the adhesive 48 may be distributed more in one side of the trenches 50 than the other. Thinning of the semiconductor wafer 44 is also illustrated. Thinning can be performed by any methods known in the art, such as, by non-limiting example, backgrinding, polishing, lapping, chemical mechanical polishing, etching, any combination thereof, and any other methods of thinning a planar surface. Through silicon vias 52 may also be added to the semiconductor wafer 44. The various process steps used to form the through silicon vias may include, by non-limiting example, etching of the semiconductor wafer, formation of adhesion films inside the various vias, electroplating/electroless plating within the vias to form a contact, formation of pads, and those other process steps and processes capable of constructing a via through the thinned wafer.

[0035] Referring to FIG. 5D, singulation of the semiconductor package 54 is illustrated. Here, the singulation is performed in the middle or substantial middle of the corresponding trenches 50, or the bond line, so each package has 50% or substantially 50% of the bond line. Singulation may take place using, by non-limiting example, sawing, lasering, high pressure water jet cutting, etching, or any other process for separating the semiconductor packages. Referring to FIG. 5E, an implementation of the completed singulated package is shown 52. In various method implementations, the method may include coupling a redistribution layer 56 to each of the singulated semiconductor packages. In various implementations, the method may also include coupling a plurality of ball mounts to each redistribution layer of each of the singulated semiconductor packages. In various implementations, balls may be coupled to the ball mounts to form a ball grid array 60. In particular implementations, the method may include adding a solder mask 58 may be added to the package.

[0036] The various methods of manufacturing a semiconductor packages disclosed herein may improve the reliability of the package for application in automotive applications. Semiconductor packages manufactured using the disclosed methods and structures may demonstrate increased adhesion force against the stress in the X-axis and the Y-axis during thermal shock reliability testing. The trench process on the silicon wafer and the glass wafer may also let the dam adhesive fill the gap without needing any changes to the design rules or use of wide scribe lines, thus maintaining the same gross die per wafer performance.

[0037] In places where the description above refers to particular implementations of semiconductor packages and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor packages.