INTELLIGENT SLICE CACHING

Abstract

Systems and methods for intelligent slice caching in a dispersed storage network. The methods include determining a minimum slice access rate for encoded data slices to be stored, determining a least access rate of a least accessed encoded data slice stored, determining an estimated access rate for an encoded data slice and determining whether to store the encoded data slice in small fast memory as a cached encoded data slice based on the minimum slice access rate, the least access rate, and the estimated access rate. The method further includes facilitating storage of the encoded data slice in small fast memory. The method may also include updating the minimum slice access rate and transferring an encoded data slice stored in small fast memory to large slow memory when an actual access rate is less than the minimum slice access rate or is less than the least access rate.

Claims

1. A method of storing data in a dispersed storage network, the dispersed storage network including a plurality of dispersed storage units, the method comprising: determining a minimum slice access rate for storing slices in a first memory of a first dispersed storage unit of the plurality of dispersed storage units; determining a least access rate of a least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units; determining an estimated access rate for an encoded data slice to be stored; determining whether to store the encoded data slice to be stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units based on the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units, the least access rate of the least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units and the estimated access rate for the encoded data slice to be stored to produce a determination; and storing the encoded data slice to be stored in the first memory based on the determination.

2. The method of claim 1, wherein first memory includes a small fast memory and wherein the first dispersed storage unit of the plurality of dispersed storage units further includes a second memory, the second memory including a large slow memory.

3. The method of claim 2 wherein the step of storing the encoded data slice to be stored in the first memory based on the determination includes transferring the encoded data slice from the second memory to the first memory.

4. The method of claim 1, wherein the step of determining the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units is based on one or more of a historical access rate, a memory wear factor and a capacity level of the first memory.

5. The method of claim 4, wherein the memory wear factor includes a maximum number of writes per unit of time.

6. The method of claim 1, wherein the step of determining the least access rate of the least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units includes one or more of measuring access rates of encoded data slices stored in the first memory and identifying a minimum access rate.

7. The method of claim 1, wherein the step of determining the estimated access rate for the encoded data slice to be stored includes one or more of identifying the encoded data slice to be stored, measuring an actual access rate and receiving the estimated access rate.

8. The method of claim 1 wherein the step of determining whether to store the encoded data slice to be stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units includes indicating to store the encoded data slice to be stored in the first memory when the estimated access rate is greater than the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units and the estimated access rate is greater than the least access rate of the least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units.

9. A first dispersed storage unit for use in a dispersed storage network, the dispersed storage network including a plurality of dispersed storage units, the first dispersed storage unit comprising: a communications interface; a first memory; a second memory; a computer processor; where the second memory includes instructions for causing the computer processor to: determine a minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units; determine a least access rate of a least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units; determine an estimated access rate for an encoded data slice to be stored; determine whether to store the encoded data slice to be stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units based on the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units, the least access rate of the least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units and the estimated access rate for the encoded data slice to be stored to produce a determination; and store the encoded data slice to be stored in the first memory based on the determination.

10. The first dispersed storage unit of claim 9, wherein first memory includes a small fast memory and wherein the second memory includes a large slow memory.

11. The first dispersed storage unit of claim 10, wherein the second memory includes instructions for further causing the computer processor to transfer the encoded data slice from the second memory to the first memory.

12. The first dispersed storage unit of claim 9, wherein the instructions for causing the computer processor to determine the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units are based on one or more of a historical access rate, a memory wear factor and a capacity level of the first memory.

13. The first dispersed storage unit of claim 12, wherein the memory wear factor includes a maximum number of writes per unit of time.

14. The first dispersed storage unit of claim 9, wherein the second memory includes instructions for further causing the computer processor to, one or more of, measure access rates of encoded data slices stored in the first memory and identify a minimum access rate.

15. The first dispersed storage unit of claim 9, wherein the second memory includes instructions for further causing the computer processor to, one or more, of identify the encoded data slice to be stored, measure an actual access rate and receive the estimated access rate.

16. The first dispersed storage unit of claim 9, wherein the second memory includes instructions for further causing the computer processor to indicate to store the encoded data slice to be stored in the first memory when the estimated access rate is greater than the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units and the estimated access rate is greater than the least access rate of the least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units.

17. A dispersed storage network comprising: a plurality of dispersed storage units; wherein a first dispersed storage unit of the plurality of dispersed storage units includes: a communications interface; a first memory; a second memory; a computer processor; where the second memory includes instructions for causing the computer processor to: determine a minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units; determine a least access rate of a least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units; determine an estimated access rate for an encoded data slice to be stored; determine whether to store the encoded data slice to be stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units based on the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units, the least access rate of the least accessed encoded data slice stored in the first memory of the first dispersed storage unit of the plurality of dispersed storage units and the estimated access rate for the encoded data slice to be stored to produce a determination; and store the encoded data slice to be stored in the first memory based on the determination.

18. The dispersed storage network of claim 17, wherein first memory includes a small fast memory and the second memory includes a large slow memory.

19. The dispersed storage network of claim 18, wherein the second memory includes instructions for further causing the computer processor to transfer the encoded data slice from the second memory to the first memory.

20. The dispersed storage network of claim 17, wherein the instructions for causing the computer processor to determine the minimum slice access rate for storing slices in the first memory of the first dispersed storage unit of the plurality of dispersed storage units are based on one or more of a historical access rate, a memory wear factor and a capacity level of the first memory.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0011] FIG. 1 is a schematic block diagram of an embodiment of a dispersed, or distributed, storage network (DSN) in accordance with the present disclosure;

[0012] FIG. 2 is a schematic block diagram of an embodiment of a computing core in accordance with the present disclosure;

[0013] FIG. 3 is a schematic block diagram of an example of dispersed storage error encoding of data in accordance with the present disclosure;

[0014] FIG. 4 is a schematic block diagram of a generic example of an error encoding function in accordance with the present disclosure;

[0015] FIG. 5 is a schematic block diagram of a specific example of an error encoding function in accordance with the present disclosure;

[0016] FIG. 6 is a schematic block diagram of an example of slice naming information for an encoded data slice (EDS) in accordance with the present disclosure;

[0017] FIG. 7 is a schematic block diagram of an example of dispersed storage error decoding of data in accordance with the present disclosure;

[0018] FIG. 8 is a schematic block diagram of a generic example of an error decoding function in accordance with the present disclosure;

[0019] FIG. 9 is a schematic block diagram of an example of a dispersed storage network in accordance with the present disclosure;

[0020] FIG. 10A is a schematic block diagram of another embodiment of a dispersed storage network (DSN) in accordance with the present invention; and

[0021] FIG. 10B is a flowchart illustrating an example of intelligent slice caching in a dispersed storage network (DSN).

DETAILED DESCRIPTION OF THE INVENTION

[0022] FIG. 1 is a schematic block diagram of an embodiment of a dispersed, or distributed, storage network (DSN) 10 that includes a plurality of dispersed storage (DS) computing devices or processing units 12-16, a DS managing unit 18, a DS integrity processing unit 20, and a DSN memory 22. The components of the DSN 10 are coupled to a network 24, which may include one or more wireless and/or wire lined communication systems; one or more non-public intranet systems and/or public internet systems; and/or one or more local area networks (LAN) and/or wide area networks (WAN).

[0023] The DSN memory 22 includes a plurality of dispersed storage units 36 (DS units) that may be located at geographically different sites (e.g., one in Chicago, one in Milwaukee, etc.), at a common site, or a combination thereof. For example, if the DSN memory 22 includes eight dispersed storage units 36, each storage unit is located at a different site. As another example, if the DSN memory 22 includes eight storage units 36, all eight storage units are located at the same site. As yet another example, if the DSN memory 22 includes eight storage units 36, a first pair of storage units are at a first common site, a second pair of storage units are at a second common site, a third pair of storage units are at a third common site, and a fourth pair of storage units are at a fourth common site. Note that a DSN memory 22 may include more or less than eight storage units 36.

[0024] DS computing devices 12-16, the managing unit 18, and the integrity processing unit 20 include a computing core 26, and network or communications interfaces 30-33 which can be part of or external to computing core 26. DS computing devices 12-16 may each be a portable computing device and/or a fixed computing device. A portable computing device may be a social networking device, a gaming device, a cell phone, a smart phone, a digital assistant, a digital music player, a digital video player, a laptop computer, a handheld computer, a tablet, a video game controller, and/or any other portable device that includes a computing core. A fixed computing device may be a computer (PC), a computer server, a cable set-top box, a satellite receiver, a television set, a printer, a fax machine, home entertainment equipment, a video game console, and/or any type of home or office computing equipment. Note that each of the managing unit 18 and the integrity processing unit 20 may be separate computing devices, may be a common computing device, and/or may be integrated into one or more of the computing devices 12-16 and/or into one or more of the dispersed storage units 36.

[0025] Each interface 30, 32, and 33 includes software and/or hardware to support one or more communication links via the network 24 indirectly and/or directly. For example, interface 30 supports a communication link (e.g., wired, wireless, direct, via a LAN, via the network 24, etc.) between computing devices 14 and 16. As another example, interface 32 supports communication links (e.g., a wired connection, a wireless connection, a LAN connection, and/or any other type of connection to/from the network 24) between computing devices 12 and 16 and the DSN memory 22. As yet another example, interface 33 supports a communication link for each of the managing unit 18 and the integrity processing unit 20 to the network 24.

[0026] In general, and with respect to DS error encoded data storage and retrieval, the DSN 10 supports three primary operations: storage management, data storage and retrieval. More specifically computing devices 12 and 16 include a dispersed storage (DS) client module 34, which enables the computing device to dispersed storage error encode and decode data (e.g., data object 40) as subsequently described with reference to one or more of FIGS. 3-8. In this example embodiment, computing device 16 functions as a dispersed storage processing agent for computing device 14. In this role, computing device 16 dispersed storage error encodes and decodes data on behalf of computing device 14. With the use of dispersed storage error encoding and decoding, the DSN 10 is tolerant of a significant number of storage unit failures (the number of failures is based on parameters of the dispersed storage error encoding function) without loss of data and without the need for a redundant or backup copies of the data. Further, the DSN 10 stores data for an indefinite period of time without data loss and in a secure manner (e.g., the system is very resistant to unauthorized attempts at accessing or hacking the data).

[0027] The second primary function (i.e., distributed data storage and retrieval) begins and ends with a DS computing devices 12-14. For instance, if a second type of computing device 14 has data 40 to store in the DSN memory 22, it sends the data 40 to the DS computing device 16 via its interface 30. The interface 30 functions to mimic a conventional operating system (OS) file system interface (e.g., network file system (NFS), flash file system (FFS), disk file system (DFS), file transfer protocol (FTP), web-based distributed authoring and versioning (WebDAV), etc.) and/or a block memory interface (e.g., small computer system interface (SCSI), internet small computer system interface (iSCSI), etc.).

[0028] In operation, the managing unit 18 performs DS management services. For example, the managing unit 18 establishes distributed data storage parameters (e.g., vault creation, distributed storage parameters, security parameters, billing information, user profile information, etc.) for computing devices 12-16 individually or as part of a group of user devices. As a specific example, the managing unit 18 coordinates creation of a vault (e.g., a virtual memory block associated with a portion of an overall namespace of the DSN) within the DSN memory 22 for a user device, a group of devices, or for public access and establishes per vault dispersed storage (DS) error encoding parameters for a vault. The managing unit 18 facilitates storage of DS error encoding parameters for each vault by updating registry information of the DSN 10, where the registry information may be stored in the DSN memory 22, a computing device 12-16, the managing unit 18, and/or the integrity processing unit 20.

[0029] The DS error encoding parameters (e.g., or dispersed storage error coding parameters) include data segmenting information (e.g., how many segments data (e.g., a file, a group of files, a data block, etc.) is divided into), segment security information (e.g., per segment encryption, compression, integrity checksum, etc.), error coding information (e.g., pillar width, decode threshold, read threshold, write threshold, etc.), slicing information (e.g., the number of encoded data slices that will be created for each data segment); and slice security information (e.g., per encoded data slice encryption, compression, integrity checksum, etc.).

[0030] The managing unit 18 creates and stores user profile information (e.g., an access control list (ACL)) in local memory and/or within memory of the DSN memory 22. The user profile information includes authentication information, permissions, and/or the security parameters. The security parameters may include encryption/decryption scheme, one or more encryption keys, key generation scheme, and/or data encoding/decoding scheme.

[0031] The managing unit 18 creates billing information for a particular user, a user group, a vault access, public vault access, etc. For instance, the managing unit 18 tracks the number of times a user accesses a non-public vault and/or public vaults, which can be used to generate per-access billing information. In another instance, the managing unit 18 tracks the amount of data stored and/or retrieved by a user device and/or a user group, which can be used to generate per-data-amount billing information. As will be described in more detail in conjunction with FIGS. 10A and 10B, usage can be determined by a managing unit 18 on a byte-hour basis.

[0032] As another example, the managing unit 18 performs network operations, network administration, and/or network maintenance. Network operations includes authenticating user data allocation requests (e.g., read and/or write requests), managing creation of vaults, establishing authentication credentials for user devices, adding/deleting components (e.g., user devices, storage units, and/or computing devices with a DS client module 34) to/from the DSN 10, and/or establishing authentication credentials for the storage units 36. Network operations can further include monitoring read, write and/or delete communications attempts, which attempts could be in the form of requests. Network administration includes monitoring devices and/or units for failures, maintaining vault information, determining device and/or unit activation status, determining device and/or unit loading, and/or determining any other system level operation that affects the performance level of the DSN 10. Network maintenance includes facilitating replacing, upgrading, repairing, and/or expanding a device and/or unit of the DSN 10.

[0033] To support data storage integrity verification within the DSN 10, the integrity processing unit 20 (and/or other devices in the DSN 10 such as managing unit 18) may assess and perform rebuilding of bad or missing encoded data slices. At a high level, the integrity processing unit 20 performs rebuilding by periodically attempting to retrieve/list encoded data slices, and/or slice names of the encoded data slices, from the DSN memory 22. Retrieved encoded slices are assessed and checked for errors due to data corruption, outdated versioning, etc. If a slice includes an error, it is flagged as a bad or corrupt slice. Encoded data slices that are not received and/or not listed may be flagged as missing slices. Bad and/or missing slices may be subsequently rebuilt using other retrieved encoded data slices that are deemed to be good slices in order to produce rebuilt slices. A multi-stage decoding process may be employed in certain circumstances to recover data even when the number of valid encoded data slices of a set of encoded data slices is less than a relevant decode threshold number. The rebuilt slices may then be written to DSN memory 22. Note that the integrity processing unit 20 may be a separate unit as shown, included in DSN memory 22, included in the computing device 16, managing unit 18, stored on a DS unit 36, and/or distributed among multiple storage units 36.

[0034] FIG. 2 is a schematic block diagram of an embodiment of a computing core 26 that includes a processing module 50, a memory controller 52, main memory 54, a video graphics processing unit 55, an input/output (IO) controller 56, a peripheral component interconnect (PCI) interface 58, an IO interface module 60, at least one IO device interface module 62, a read only memory (ROM) basic input output system (BIOS) 64, and one or more memory interface modules. The one or more memory interface module(s) includes one or more of a universal serial bus (USB) interface module 66, a host bus adapter (HBA) interface module 68, a network interface module 70, a flash interface module 72, a hard drive interface module 74, and a DSN interface module 76.

[0035] The DSN interface module 76 functions to mimic a conventional operating system (OS) file system interface (e.g., network file system (NFS), flash file system (FFS), disk file system (DFS), file transfer protocol (FTP), web-based distributed authoring and versioning (WebDAV), etc.) and/or a block memory interface (e.g., small computer system interface (SCSI), internet small computer system interface (iSCSI), etc.). The DSN interface module 76 and/or the network interface module 70 may function as one or more of the interface 30-33 of FIG. 1. Note that the IO device interface module 62 and/or the memory interface modules 66-76 may be collectively or individually referred to as IO ports.

[0036] FIG. 3 is a schematic block diagram of an example of dispersed storage error encoding of data. When a computing device 12 or 16 has data to store it disperse storage error encodes the data in accordance with a dispersed storage error encoding process based on dispersed storage error encoding parameters. The dispersed storage error encoding parameters include an encoding function (e.g., information dispersal algorithm, Reed-Solomon, Cauchy Reed-Solomon, systematic encoding, non-systematic encoding, on-line codes, etc.), a data segmenting protocol (e.g., data segment size, fixed, variable, etc.), and per data segment encoding values. The per data segment encoding values include a total, or pillar width, number (T) of encoded data slices per encoding of a data segment (i.e., in a set of encoded data slices); a decode threshold number (D) of encoded data slices of a set of encoded data slices that are needed to recover the data segment; a read threshold number (R) of encoded data slices to indicate a number of encoded data slices per set to be read from storage for decoding of the data segment; and/or a write threshold number (W) to indicate a number of encoded data slices per set that must be accurately stored before the encoded data segment is deemed to have been properly stored. The dispersed storage error encoding parameters may further include slicing information (e.g., the number of encoded data slices that will be created for each data segment) and/or slice security information (e.g., per encoded data slice encryption, compression, integrity checksum, etc.).

[0037] In the present example, Cauchy Reed-Solomon has been selected as the encoding function (a generic example is shown in FIG. 4 and a specific example is shown in FIG. 5); the data segmenting protocol is to divide the data object into fixed sized data segments; and the per data segment encoding values include: a pillar width of 5, a decode threshold of 3, a read threshold of 4, and a write threshold of 4. In accordance with the data segmenting protocol, the computing device 12 or 16 divides the data (e.g., a file (e.g., text, video, audio, etc.), a data object, or other data arrangement) into a plurality of fixed sized data segments (e.g., 1 through Y of a fixed size in range of Kilo-bytes to Tera-bytes or more). The number of data segments created is dependent of the size of the data and the data segmenting protocol.

[0038] The computing device 12 or 16 then disperse storage error encodes a data segment using the selected encoding function (e.g., Cauchy Reed-Solomon) to produce a set of encoded data slices. FIG. 4 illustrates a generic Cauchy Reed-Solomon encoding function, which includes an encoding matrix (EM), a data matrix (DM), and a coded matrix (CM). The size of the encoding matrix (EM) is dependent on the pillar width number (T) and the decode threshold number (D) of selected per data segment encoding values. To produce the data matrix (DM), the data segment is divided into a plurality of data blocks and the data blocks are arranged into D number of rows with Z data blocks per row. Note that Z is a function of the number of data blocks created from the data segment and the decode threshold number (D). The coded matrix is produced by matrix multiplying the data matrix by the encoding matrix.

[0039] FIG. 5 illustrates a specific example of Cauchy Reed-Solomon encoding with a pillar number (T) of five and decode threshold number of three. In this example, a first data segment is divided into twelve data blocks (D1-D12). The coded matrix includes five rows of coded data blocks, where the first row of X11-X14 corresponds to a first encoded data slice (EDS 1_1), the second row of X21-X24 corresponds to a second encoded data slice (EDS 2_1), the third row of X31-X34 corresponds to a third encoded data slice (EDS 3_1), the fourth row of X41-X44 corresponds to a fourth encoded data slice (EDS 4_1), and the fifth row of X51-X54 corresponds to a fifth encoded data slice (EDS 5_1). Note that the second number of the EDS designation corresponds to the data segment number. In the illustrated example, the value X11=aD1+bD5+cD9, X12=aD2+bD6+cD10, . . . X53=mD3+nD7+oD11, and X54=mD4+nD8+oD12.

[0040] Returning to the discussion of FIG. 3, the computing device also creates a slice name (SN) for each encoded data slice (EDS) in the set of encoded data slices. A typical format for a slice name 80 is shown in FIG. 6. As shown, the slice name (SN) 80 includes a pillar number of the encoded data slice (e.g., one of 1-T), a data segment number (e.g., one of 1-Y), a vault identifier (ID), a data object identifier (ID), and may further include revision level information of the encoded data slices. The slice name functions as at least part of a DSN address for the encoded data slice for storage and retrieval from the DSN memory 22.

[0041] As a result of encoding, the computing device 12 or 16 produces a plurality of sets of encoded data slices, which are provided with their respective slice names to the storage units for storage. As shown, the first set of encoded data slices includes EDS 1_1 through EDS 5_1 and the first set of slice names includes SN 1_1 through SN 5_1 and the last set of encoded data slices includes EDS 1_Y through EDS 5_Y and the last set of slice names includes SN 1_Y through SN 5_Y.

[0042] FIG. 7 is a schematic block diagram of an example of dispersed storage error decoding of a data object that was dispersed storage error encoded and stored in the example of FIG. 4. In this example, the computing device 12 or 16 retrieves from the storage units at least the decode threshold number of encoded data slices per data segment. As a specific example, the computing device retrieves a read threshold number of encoded data slices.

[0043] In order to recover a data segment from a decode threshold number of encoded data slices, the computing device uses a decoding function as shown in FIG. 8. As shown, the decoding function is essentially an inverse of the encoding function of FIG. 4. The coded matrix includes a decode threshold number of rows (e.g., three in this example) and the decoding matrix in an inversion of the encoding matrix that includes the corresponding rows of the coded matrix. For example, if the coded matrix includes rows 1, 2, and 4, the encoding matrix is reduced to rows 1, 2, and 4, and then inverted to produce the decoding matrix.

[0044] FIG. 9 is a diagram of an example of a dispersed storage network. The dispersed storage network includes a DS (dispersed storage) client module 34 (which may be in DS computing devices 12 and/or 16 of FIG. 1), a network 24, and a plurality of DS units 36-1 . . . 36-n (which may be storage units 36 of FIG. 1 and which form at least a portion of DS memory 22 of FIG. 1), a DSN managing unit 18, and a DS integrity verification module (not shown). The DS client module 34 includes an outbound DS processing section 81 and an inbound DS processing section 82. Each of the DS units 36-1 . . . 36-n includes a controller 86, a processing module 84 (e.g. computer processor) including a communications interface for communicating over network 24 (not shown), memory 88, a DT (distributed task) execution module 90, and a DS client module 34.

[0045] In an example of operation, the DS client module 34 receives data 92. The data 92 may be of any size and of any content, where, due to the size (e.g., greater than a few Terabytes), the content (e.g., secure data, etc.), and/or concerns over security and loss of data, distributed storage of the data is desired. For example, the data 92 may be one or more digital books, a copy of a company's emails, a large-scale Internet search, a video security file, one or more entertainment video files (e.g., television programs, movies, etc.), data files, and/or any other large amount of data (e.g., greater than a few Terabytes).

[0046] Within the DS client module 34, the outbound DS processing section 81 receives the data 92. The outbound DS processing section 81 processes the data 92 to produce slice groupings 96. As an example of such processing, the outbound DS processing section 81 partitions the data 92 into a plurality of data partitions. For each data partition, the outbound DS processing section 81 dispersed storage (DS) error encodes the data partition to produce encoded data slices and groups the encoded data slices into a slice grouping 96.

[0047] The outbound DS processing section 81 then sends, via the network 24, the slice groupings 96 to the DS units 36-1 . . . 36-n of the DSN memory 22 of FIG. 1. For example, the outbound DS processing section 81 sends slice group 1 to DS storage unit 36-1. As another example, the outbound DS processing section 81 sends slice group #n to DS unit #n.

[0048] In one example of operation, the DS client module 34 requests retrieval of stored data within the memory of the DS units 36. In this example, the task 94 is retrieve data stored in the DSN memory 22. Accordingly, and according to one embodiment, the outbound DS processing section 81 converts the task 94 into a plurality of partial tasks 98 and sends the partial tasks 98 to the respective DS storage units 36-1 . . . 36-n.

[0049] In response to the partial task 98 of retrieving stored data, a DS storage unit 36 identifies the corresponding encoded data slices 99 and retrieves them. For example, DS unit #1 receives partial task #1 and retrieves, in response thereto, retrieved slices #1. The DS units 36 send their respective retrieved slices 99 to the inbound DS processing section 82 via the network 24.

[0050] The inbound DS processing section 82 converts the retrieved slices 99 into data 92. For example, the inbound DS processing section 82 de-groups the retrieved slices 99 to produce encoded slices per data partition. The inbound DS processing section 82 then DS error decodes the encoded slices per data partition to produce data partitions. The inbound DS processing section 82 de-partitions the data partitions to recapture the data 92.

[0051] In one example of operation, the DSN of FIG. 1 is used to perform intelligent slice caching. Explanations of this process are set out below in conjunction with FIGS. 10A and 10B. While described in the context of functionality provided by DS units 36, this functionality may be implemented utilizing any module and/or unit of a dispersed storage network (DSN) including the DS Processing Unit 16, the DS Managing Unit 18 and/or the Integrity Processing Unit 20, shown in FIG. 1.

[0052] In a DS unit, with a relatively, smaller high speed memory and a relatively larger low speed memory, moving more frequently accessed objects to the high speed memory can increase performance and reduce latency. However, for some forms of memory, frequent writes can cause degradation and wear. Therefore, in a DS unit utilizing such a highspeed, but wear-sensitive form of memory, more intelligent decision making may be utilized to optimally cache items in the high speed memory so as to reduce wear and keep it within an acceptable boundary. The effectiveness of a placement of a slice in the high speed memory of a DS unit can, in one example, be measured in terms of the number of times it is accessed per time frame or period that slice is moved into the high speed memory, and before it is replaced with something else. One mechanism to achieve these goals is to set a minimum bar which a slice's access rate must exceed before it can be moved into the high speed memory. This bar can be raised or lowered, such that entry to, and eviction from, the high speed memory's cache can be lowered or increased to stay within the limits of the high speed, but wear-sensitive memory device. Once the bar is set, a slice's access patterns may be measured according to: Frequency of access for the slice; and the Length of time the slice last remained in the cache. According to one example, when a slice's access frequency exceeds that of the least frequently accessed slice in the cache, and the rate exceeds the minimum bar for moving an item into the cache, then the slice is moved to the high speed memory such that future access requests can be satisfied from that memory.

[0053] In another example, this same logic described above can be applied in a DS processing unit 16, only for the ds processing unit 16 it is applied to restored objects, rather than encoded data slices. Also, when load balancers/requesters know that a DS processing unit is using such a caching logic, it may purposely direct repeated requests for that same object to the same DS processing unit to maximize use of its cache, and likewise a DS processing unit requesting slices from a DS unit can do the same (by reusing the same threshold DS units for reading those slices when the slices are repeatedly requested).

[0054] FIG. 10A is a schematic block diagram of another embodiment of a dispersed storage network that includes a set of storage units 36-1, 36-2 . . . 36-n, the network 24 of FIG. 1, and the distributed storage (DS) processing unit 16 of FIG. 1. Each storage unit includes a respective computer processor or processing module 84 of FIG. 9 (84-1, 84-2 . . . 84-n), a small fast memory (88-1-1, 88-2-1 . . . 88-n1), and a large slow memory (88-1-2, 88-2-2 . . . 88-n2). According to this example the large slow memory has more memory capacity than the small fast memory and the small fast memory has a faster access latency times than the large slow memory. Each of the small fast memory and the large slow memory may be implemented utilizing the memory 88 of FIG. 9. For example, the small fast memory is implemented utilizing solid state memory technology and the large slow memory is implemented utilizing magnetic disk drive technology. Each storage unit may be implemented utilizing the DS execution unit 36 of FIG. 1. According to one example, the DSN functions to optimize utilization of storage memory.

[0055] In an example of operation of the optimizing of utilization of the storage memory, the processing modules 84-1, 84-2 . . . 84-n (as the case may be) determine a minimum slice access rate for slices (500-1, 500-2 and 500-n) to be stored in the respective small fast memory 88-1-1, 88-2-1 . . . 88-n1. The determining may be based on one or more of a historical access rate, an estimated access rate for one or more encoded data slices, a memory wear factor (i.e., maximum number of write per unit of time), and a capacity level of the small fast memory. Having determined the minimum slice access rate, the respective processing module 84-1, 84-2 . . . 84-n determines a respective least access rate of a least accessed encoded data slice stored in the respective small fast memory. For example, the respective processing module 84-1, 84-2 . . . 84-n measures access rates of encoded data slices stored within the small fast memory and identifies a minimum access rate as the least access rate.

[0056] Having determined the least access rate, the respective processing module 84-1, 84-2 . . . 84-n determines an estimated access rate for an encoded data slice. The determining includes at least one of identifying the slice identifying within a memory of an associated storage unit, measuring an actual access rate, and receiving the estimated access rate. For example, the processing module 84-1 of the storage unit 1 receives a write slice request that includes an encoded data slice 500-1 of a set of encoded data slices for storage 500-1, 500-2 . . . 500-n and an estimated access rate for the encoded data slice 500-1, where the DS processing unit 16 generates the set of encoded data slices, and sends, via the network 24, the set of encoded data slices to the set of storage units.

[0057] Having determined the estimated access rate for the encoded data slice, the respective processing module 84-1, 84-2 . . . 84-n determines whether to store (e.g., new to store, maintain storage) respective encoded data slice 500-1, 500-2 . . . 500-n in the respective small fast memory 88-1-1, 88-2-1 . . . 88-n1 as a cached encoded data slice based on the minimum slice access rate, the least access rate, and the estimated access rate. For example, the processing module 84-1 indicates to store the encoded data slice 500-1 in the small fast memory 88-1-1 of storage unit 36-1 when the estimated access rate is greater than the minimum slice access rate and is greater than the least access rate.

[0058] When determining to store a respective encoded data slice in a respective small fast memory 88-1-1, 88-2-1 . . . 88-n1, the respective processing module 84-1, 84-2 . . . 84-n facilitates storage of the respective encoded data slice 500-1, 500-2 . . . 500-n of a small fast memory. The facilitating includes one of the processing module 84 storing a received encoded data slice of a small fast memory and transferring the encoded data slice from the large slow memory to the small fast memory.

[0059] FIG. 10B is a flowchart illustrating an example of optimizing utilization of storage memory. The method includes a step 600 where a processing module (e.g., of a storage unit) determines a minimum slice access rate for encoded data slices to be stored in a small fast memory. The determining may be based on one or more of historical access rates, a memory wear factor, and a capacity level of the small fast memory. The method continues at a step 602 where the processing module determines a least access rate of a least accessed encoded data slice stored in the small fast memory. The determining includes one or more of measuring access rates of encoded data slices stored within the small fast memory and identifying a minimum access rate as the least access rate.

[0060] The method continues at the step 604 where the processing module determines an estimated access rate for an encoded data slice. The determining includes one or more of identifying the encoded data slice (i.e., receiving, identifying within a memory the storage unit), measuring an actual access rate, and receiving the estimated access rate. The method continues at the step 606 where the processing module determines whether to store the encoded data slice in the small fast memory as a cached encoded data slice based on the minimum slice access rate, the least access rate, and the estimated access rate. According to one example, step 606 results in producing a determination. For example, the processing module indicates to store the encoded data slice in the small fast memory when the estimated access rate is greater than the minimum slice access rate and is greater than the least access rate.

[0061] When storing the encoded data slice of a small fast memory, the method continues at the step 608 where the processing module facilitates storage of the encoded data slice in the small fast memory. The facilitating includes one of storing the received encoded data slice in the small fast memory and transferring the encoded data slice from a large slow memory to the small fast memory. Alternatively, or in addition to, the processing module updates the minimum slice access rate and transfers and encoded data slice stored in small fast memory to the large slow memory when an actual access rate is less than the minimum slice access rate or is less than the least access rate.

[0062] As may be used herein, the terms substantially and approximately provides an industry-accepted tolerance for its corresponding term and/or relativity between items. Such an industry-accepted tolerance ranges from less than one percent to fifty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. Such relativity between items ranges from a difference of a few percent to magnitude differences. As may also be used herein, the term(s) configured to, operably coupled to, coupled to, and/or coupling includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for an example of indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as coupled to. As may even further be used herein, the term configured to, operable to, coupled to, or operably coupled to indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term associated with, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item.

[0063] As may be used herein, the term compares favorably, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal A has a greater magnitude than signal B, a favorable comparison may be achieved when the magnitude of signal A is greater than that of signal B or when the magnitude of signal B is less than that of signal A. As may be used herein, the term compares unfavorably, indicates that a comparison between two or more items, signals, etc., fails to provide the desired relationship.

[0064] As may also be used herein, the terms processing module, processing circuit, processor, and/or processing unit may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, and/or processing unit may be, or further include, memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processing module, module, processing circuit, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture.

[0065] One or more embodiments have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality.

[0066] To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claims. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.

[0067] In addition, a flow diagram may include a start and/or continue indication. The start and continue indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with other routines. In this context, start indicates the beginning of the first step presented and may be preceded by other activities not specifically shown. Further, the continue indication reflects that the steps presented may be performed multiple times and/or may be succeeded by other activities not specifically shown. Further, while a flow diagram indicates a particular ordering of steps, other orderings are likewise possible provided that the principles of causality are maintained.

[0068] The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from Figure to Figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones.

[0069] Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art.

[0070] The term module is used in the description of one or more of the embodiments. A module implements one or more functions via a device such as a processor or other processing device or other hardware that may include or operate in association with a memory that stores operational instructions. A module may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules.

[0071] As may further be used herein, a computer readable memory includes one or more memory elements. A memory element may be a separate memory device, multiple memory devices, or a set of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. The memory device may be in a form a solid state memory, a hard drive memory, cloud memory, thumb drive, server memory, computing device memory, and/or other physical medium for storing digital information. A computer readable memory/storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0072] While particular combinations of various functions and features of the one or more embodiments have been expressly described herein, other combinations of these features and functions are likewise possible. The present disclosure is not limited by the particular examples disclosed herein and expressly incorporates these other combinations.