METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

20170162564 · 2017-06-08

Assignee

Rohm Co., Ltd. (Kyoto, JP)

Inventors

Cpc classification

International classification

Abstract

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

Claims

1. A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, the method comprising the steps of: forming a second conductive-type SiC base layer on a first surface of a second conductive-type SiC substrate having the first surface and a second surface and defining a drain region of the SiC-MOSFET; selectively etching the second surface of the SiC substrate to form a trench in the SiC substrate; implanting first conductive-type impurities into a bottom surface of the trench to form a collector region in the bottom surface; selectively implanting first conductive-type impurities into the surface of the SiC base layer to form a channel region in a surficial portion of the SiC base layer; and selectively implanting second conductive-type impurities into the surface of the SiC base layer to form an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

2. A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, the method comprising the steps of: forming a second conductive-type SiC base layer on a first surface of a second conductive-type SiC substrate having the first surface and a second surface; selectively etching the second surface of the SiC substrate to form a trench in the SiC substrate; selectively implanting first conductive-type impurities into a bottom surface of the trench to form a collector region in the bottom surface; selectively implanting second conductive-type impurities into the bottom surface of the trench to form a drain region in the bottom surface; selectively implanting first conductive-type impurities into the surface of the SiC base layer to form a channel region in a surficial portion of the SiC base layer; and selectively implanting second conductive-type impurities into the surface of the SiC base layer to form an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

3. The semiconductor device manufacturing method according to claim 1, wherein the step of forming the trench includes the step of etching until the SiC base layer is exposed to the trench.

4. The semiconductor device manufacturing method according to claim 1, further comprising, a step of implanting second conductive-type impurities into the vicinity of the first surface of the SiC substrate before the step of forming the SiC base layer.

5. The semiconductor device manufacturing method according to claim 1, wherein the step of forming the SiC base layer includes the steps of forming a first high-concentration impurity layer on the first surface of the SiC substrate and forming a drift layer on the first high-concentration impurity layer so as to have an impurity concentration relatively lower than that of the first high-concentration impurity layer, and wherein the step of forming the trench includes the step of selectively forming a trench penetrating through the SiC substrate and the high-concentration impurity layer to reach the drift layer, the method further comprising, before the step of forming the collector region, the step of implanting second conductive-type impurities into the bottom surface of the trench to form a second high-concentration impurity layer in the bottom surface to thereby form a buffer layer in which the second high-concentration impurity layer and the first high-concentration impurity layer are integrated.

6. The semiconductor device manufacturing method according to claim 2, wherein the step of forming the trench includes the step of etching until the SiC base layer is exposed to the trench.

7. The semiconductor device manufacturing method according to claim 2, further comprising, a step of implanting second conductive-type impurities into the vicinity of the first surface of the SiC substrate before the step of forming the SiC base layer.

8. The semiconductor device manufacturing method according to claim 2, wherein the step of forming the SiC base layer includes the steps of forming a first high-concentration impurity layer on the first surface of the SiC substrate and forming a drift layer on the first high-concentration impurity layer so as to have an impurity concentration relatively lower than that of the first high-concentration impurity layer, and wherein the step of forming the trench includes the step of selectively forming a trench penetrating through the SiC substrate and the high-concentration impurity layer to reach the drift layer, the method further comprising, before the step of forming the collector region, the step of implanting second conductive-type impurities into the bottom surface of the trench to form a second high-concentration impurity layer in the bottom surface to thereby form a buffer layer in which the second high-concentration impurity layer and the first high-concentration impurity layer are integrated.

9. The semiconductor device manufacturing method according to claim 1, wherein a plurality of the trenches are formed in a striped manner.

10. The semiconductor device manufacturing method according to claim 1, wherein a deepest portion of the trench is at a position nearer the surface of the SiC base layer with respect to an interface between the SiC substrate and the SiC base layer.

11. The semiconductor device manufacturing method according to claim 1, wherein a deepest portion of the trench is at a position nearer the second surface of the SiC substrate with respect to an interface between the SiC substrate and the SiC base layer.

12. The semiconductor device manufacturing method according to claim 2, wherein a plurality of the trenches are formed in a striped manner.

13. The semiconductor device manufacturing method according to claim 2, wherein a deepest portion of the trench is at a position nearer the surface of the SiC base layer with respect to an interface between the SiC substrate and the SiC base layer.

14. The semiconductor device manufacturing method according to claim 2, wherein a deepest portion of the trench is at a position nearer the second surface of the SiC substrate with respect to an interface between the SiC substrate and the SiC base layer.

15. A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, the method comprising the steps of: forming a second conductive-type SiC base layer on a first surface of a substrate having the first surface and a second surface; removing the substrate to expose a second surface of the SiC base layer; selectively implanting first conductive-type impurities into the second surface of the SiC base layer to form a collector region in the second surface; selectively implanting second conductive-type impurities into the second surface of the SiC base layer to form a drain region in the second surface; selectively implanting first conductive-type impurities into a first surface of the SiC base layer to form a channel region in a surficial portion of the SiC base layer; and selectively implanting second conductive-type impurities into the first surface of the SiC base layer to form an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0069] FIG. 1 is an external perspective view of a semiconductor package according to a first preferred embodiment of the present invention.

[0070] FIG. 2 is a circuit diagram inside the semiconductor chip shown in FIG. 1.

[0071] FIG. 3 is a schematic cross-sectional view of the semiconductor chip shown in FIG. 1.

[0072] FIG. 4A shows a step of a process for manufacturing the semiconductor chip shown in FIG. 3.

[0073] FIG. 4B shows a step following that shown in FIG. 4A.

[0074] FIG. 4C shows a step following that shown in FIG. 4B.

[0075] FIG. 4D shows a step following that shown in FIG. 4C.

[0076] FIG. 4E shows a step following that shown in FIG. 4D.

[0077] FIG. 4F shows a step following that shown in FIG. 4E.

[0078] FIG. 5 shows a first exemplary variation of the trench shown in FIG. 3.

[0079] FIG. 6 shows a second exemplary variation of the trench shown in FIG. 3.

[0080] FIG. 7 shows an exemplary variation of the gate electrode shown in FIG. 3.

[0081] FIG. 8 is a circuit diagram of an inverter circuit with the semiconductor chip shown in FIG. 3 incorporated therein.

[0082] FIG. 9 is a schematic cross-sectional view of a semiconductor chip according to a second preferred embodiment of the present invention.

[0083] FIG. 10A shows a step of a process for manufacturing the semiconductor chip shown in FIG. 9.

[0084] FIG. 10B shows a step following that shown in FIG. 10A.

[0085] FIG. 10C shows a step following that shown in FIG. 10B.

[0086] FIG. 10D shows a step following that shown in FIG. 10C.

[0087] FIG. 10E shows a step following that shown in FIG. 10D.

[0088] FIG. 10F shows a step following that shown in FIG. 10E.

[0089] FIG. 10G shows a step following that shown in FIG. 10F.

[0090] FIG. 10H shows a step following that shown in FIG. 10G.

[0091] FIG. 11 is a schematic cross-sectional view of a semiconductor chip (of an SiC substrate segmented type) according to a third preferred embodiment of the present invention.

[0092] FIG. 12 is a schematic cross-sectional view of a semiconductor chip (of an SiC substrate segmented type) according to a fourth preferred embodiment of the present invention.

[0093] FIG. 13 is a schematic cross-sectional view of a semiconductor chip (of a trench-gate type) according to a fifth preferred embodiment of the present invention.

[0094] FIG. 14 is a schematic cross-sectional view of a semiconductor chip (of a device separated type) according to a sixth preferred embodiment of the present invention.

[0095] FIG. 15 is a schematic plan view of a semiconductor chip according to a seventh preferred embodiment of the present invention.

[0096] FIG. 16 is a schematic bottom view of the semiconductor chip shown in FIG. 15.

[0097] FIG. 17 shows an exemplary variation about the stripe direction of the collector region shown in FIG. 16.

[0098] FIG. 18 is a schematic cross-sectional view of the semiconductor chip according to the seventh preferred embodiment of the present invention.

[0099] FIG. 19 illustrates the impurity concentration of the SiC substrate and the SiC base layer.

[0100] FIG. 20A shows a step of a process for manufacturing the semiconductor chip shown in FIG. 18.

[0101] FIG. 20B shows a step following that shown in FIG. 20A.

[0102] FIG. 20C shows a step following that shown in FIG. 20B.

[0103] FIG. 20D shows a step following that shown in FIG. 20C.

[0104] FIG. 21 is a schematic cross-sectional view of a semiconductor chip according to an eighth preferred embodiment of the present invention.

[0105] FIG. 22A shows a step of a process for manufacturing the semiconductor chip shown in FIG. 21.

[0106] FIG. 22B shows a step following that shown in FIG. 22A.

[0107] FIG. 22C shows a step following that shown in FIG. 22B.

[0108] FIG. 22D shows a step following that shown in FIG. 22C.

[0109] FIG. 23 is a schematic cross-sectional view of a semiconductor chip according to a ninth preferred embodiment of the present invention.

[0110] FIG. 24A shows a step of a process for manufacturing the semiconductor chip shown in FIG. 23.

[0111] FIG. 24B shows a step following that shown in FIG. 24A.

[0112] FIG. 24C shows a step following that shown in FIG. 24B.

[0113] FIG. 24D shows a step following that shown in FIG. 24C.

[0114] FIG. 24E shows a step following that shown in FIG. 24D.

[0115] FIG. 24F shows a step following that shown in FIG. 24E.

MODES FOR CARRYING OUT THE INVENTION

[0116] Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.

[0117] FIG. 1 is an external perspective view of a semiconductor package 1 according to a first preferred embodiment of the present invention. FIG. 2 is a circuit diagram inside the semiconductor chip 8 shown in FIG. 1.

[0118] The semiconductor package 1, which serves as a semiconductor device, includes a flattened rectangular parallelepiped resin package 2, a gate terminal 3 (G), an emitter terminal 4 (E), and a collector terminal 5 (C) encapsulated in the resin package 2.

[0119] The three terminals 3 to 5 are each formed of a metal plate in a predetermined shape. In this preferred embodiment, the collector terminal 5 is formed in a shape including a square island 6 and an elongated rectangular terminal portion 7 extending linearly from a side of the island 6. The gate terminal 3 and the emitter terminal 4 are formed in approximately the same shape as the terminal portion 7 of the collector terminal 5 and disposed parallel with each other on one and the other sides of the terminal portion 7 of the collector terminal 5 in a manner sandwiching the terminal portion 7 of the collector terminal 5.

[0120] The semiconductor chip 8 is placed on the collector terminal 5 (in a central portion of the island 6). An IGBT 9 (Insulated Gate Bipolar Semiconductor), a MOSFET 11 incorporating a body diode 10 (pn-Di), and a Schottky barrier diode 12 (SBD) are mounted on the semiconductor chip 8. That is, the three devices, IGBT 9, MOSFET 11, and Schottky barrier diode 12, which serve a switching function, are mounted on the single semiconductor chip 8, and the semiconductor chip 8 is supported on the island 6 of the collector terminal 5.

[0121] As shown in FIG. 2, the MOSFET 11, the body diode 10, and the Schottky barrier diode 12 are connected in parallel to the IGBT 9 in the semiconductor chip 8.

[0122] Specifically, the source (S) of the MOSFET 11, the anode (A) of the body diode 10, and the anode (A) of the Schottky barrier diode 12 are respectively connected to the emitter (E) of the IGBT 9. The drain (D) of the MOSFET 11, the cathode (K) of the body diode 10, and the cathode (K) of the Schottky barrier diode 12 are respectively connected to the collector (C) of the IGBT 9. The gate (G) of the MOSFET 11 is connected to the gate (G) of the IGBT 9.

[0123] The gate (G) of the IGBT 9 is connected to the gate terminal 3 using a bonding wire 13, and the emitter (E) of the IGBT 9 is connected to the emitter terminal 4 using a bonding wire 14. The collector (C) of the IGBT 9 is connected to the island 6 of the collector terminal 5.

[0124] The resin package 2 then encapsulates the semiconductor chip 8, the bonding wires 13 and 14, the whole of the island 6 and a portion of the terminal portion 7 of the collector terminal 5, a portion of the gate terminal 3, and a portion of the emitter terminal 4. The rest of the terminal portion 7 of the collector terminal 5, the gate terminal 3, and the emitter terminal 4 are exposed through a side surface of the resin package 2.

[0125] In addition, the IGBT 9, the MOSFET 11 incorporating the body diode 10, and the Schottky barrier diode 12 may be integrated into the semiconductor chip 8 (single chip) indicated by the solid line in FIG. 1 (i.e., exist on the same chip) or may be provided separately as an IGBT chip 15, a MOSFET chip 16 (incorporating the body diode 10), and a Schottky barrier diode chip 17 indicated by the broken line in FIG. 1 as long as it is capable of configuring the circuit shown in FIG. 2.

[0126] In the latter case, the MOSFET 11, the body diode 10, and the Schottky barrier diode 12 can be connected in parallel to the IGBT 9, as shown in FIG. 2, by connecting the collector (C) of the IGBT chip 15, the drain (D) of the MOSFET chip 16, and the cathode (K) of the Schottky barrier diode chip 17 to the island 6 of the collector terminal 5, connecting the emitter (E) of the IGBT chip 15, the source (S) of the MOSFET chip 16, and the anode (A) of the Schottky barrier diode chip 17 to the emitter terminal 4 using bonding wires 18 to 20 respectively, and connecting the gate (G) of the IGBT chip 15 and the gate (G) of the MOSFET chip 16 to the gate terminal 3 using bonding wires 21 and 22 respectively.

[0127] FIG. 3 is a schematic cross-sectional view of the semiconductor chip 8 shown in FIG. 1.

[0128] The semiconductor chip 8 includes an SiC (silicon carbide) semiconductor layer having a first surface 24 and a second surface 25, an emitter electrode 26 connected to the first surface 24 of the SiC semiconductor layer 23, and a collector electrode 27 connected to the second surface 25 of the SiC semiconductor layer 23, and is supported on the collector terminal 5 by bonding the collector electrode 27 and the collector terminal 5 (island 6) with the emitter electrode 26 being directed upward. The bonding wire 14 shown in FIG. 1 is connected to the emitter electrode 26.

[0129] In the SiC semiconductor layer 23, multiple impurity regions constituting the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12 are formed and sandwiched vertically between the emitter electrode 26 and the collector electrode 27. The emitter electrode 26 and the collector electrode 27 are shared among the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12. That is, the emitter electrode 26 and the collector electrode 27 are external electrodes common to the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12. In the MOSFET 11, the emitter electrode 26 serves as a source electrode 28 and the collector electrode 27 serves as a drain electrode 29. On the other hand, in the Schottky barrier diode 12, the emitter electrode 26 serves as an anode electrode 30 and the collector electrode 27 serves as a cathode electrode 31. Accordingly, the SiC-IGBT 9, the SiC-MOSFET 11, and the SiC-Schottky barrier diode 12, which are constituted by multiple SiC impurity regions, are connected in parallel between the emitter electrode 26 and the collector electrode 27.

[0130] The SiC semiconductor layer 23 includes an n.sup.+-type SiC substrate 32 (with a concentration of, for example, 1.010.sup.19 to 1.010.sup.21 atoms.Math.cm.sup.3; the same applies hereinafter) defining the second surface 25 of the SiC semiconductor layer 23 and an n.sup.-type SiC base layer 33 (SiC epitaxial layer) (with a concentration of, for example, 5.010.sup.16 to 1.010.sup.14 atoms.Math.cm.sup.3; the same applies hereinafter) formed on the SiC substrate 32 and defining the first surface 24 of the SiC semiconductor layer 23.

[0131] In this preferred embodiment, the n.sup.+-type SiC substrate 32 defines a drain region 34 of the MOSFET 11 and a cathode region 35 of the Schottky barrier diode 12. Also, the SiC base layer 33 serves as a drift region in the MOSFET 11 and the Schottky barrier diode 12. In addition, the n-type impurity may be, for example, N (nitrogen), P (phosphorous), or As (arsenic).

[0132] In the SiC semiconductor layer 23, multiple trenches 36 are formed that reach from the second surface 25 to the SiC base layer 33. The multiple trenches 36 are formed in, for example, a striped manner at regular intervals. In addition, the trenches 36 may be formed in, for example, a grid manner without limiting to the striped manner.

[0133] The side surface of each trench 36 is defined by the SiC substrate 32, while the bottom surface is defined by the SiC base layer 33. P.sup.+-type collector regions 37 (collector regions 37 of the IGBT 9) (with a concentration of, for example, 1.010.sup.18 to 1.010.sup.20 atoms.Math.cm.sup.3; the same applies hereinafter) are formed on the bottom surface (second surface portion of the SiC base layer 33). In addition, the p-type impurity may be, for example, B (boron) or Al (aluminum).

[0134] The pitch between adjacent trenches 36 (trench pitch P) is preferably 1 m to 500 m. With this range of the trench pitch P, the portions between adjacent collector regions 37 (i.e., the portions where the current paths of the MOSFET 11 are formed) can be prevented from being closed by the depletion layer extending from the interface between the collector regions 37 and the SiC base layer 33.

[0135] The collector electrode 27 penetrates collectively into all the trenches 36 so as to cover the second surface 25 of the SiC substrate 32, and is connected to the SiC substrate 32 via the side surface of each trench 36, while connected to the collector regions 37 via the bottom surfaces of the respective trenches 36. The collector electrode 27 is an AlCu (alloy of aluminum and copper) electrode with a metal silicide 38 (e.g., nickel (Ni) silicide or titanium (Ti) silicide) formed in a manner contacting the inner surface (side surface and bottom surface) of each trench 36. This can bring the collector electrode 27 into ohmic contact with any target of whichever conductive type including the n.sup.+-type SiC substrate 32 and the p.sup.+-type collector regions 37.

[0136] Multiple well-like p-type channel regions 39 (with a concentration of, for example, 110.sup.16 to 110.sup.19 atoms.Math.cm.sup.3; the same applies hereinafter) are selectively formed in surficial portions of the SiC base layer 33. The multiple channel regions 39 are exposed on the first surface 24 of the SiC base layer 33 to define portions of the first surface 24. On the other hand, between the multiple channel regions 39, the SiC base layer 33 is partially exposed on the first surface 24 as a base surficial portion 40.

[0137] An n.sup.+-type emitter region 41 (emitter region 41 of the IGBT 9) is formed in a portion of the first surface 24 of each channel region 39. The emitter region 41 is exposed on the first surface 24 of the SiC base layer 33 to define a portion of the first surface 24. The emitter region 41 serves also as a source region 42 of the MOSFET 11.

[0138] In a central portion of each channel region 39, a p.sup.+-type channel contact region 43 is formed that penetrates from the first surface 24 of the SiC base layer 33 through the emitter region 41 to reach the channel region 39.

[0139] A gate insulating film 44 composed of silicon oxide (SiO.sub.2) is formed on the first surface 24 of the SiC base layer 33, and a gate electrode 45 composed of polysilicon is formed on the gate insulating film 44. The gate electrode 45 is opposed to the channel region 39, which is exposed on the first surface 24 of the SiC base layer 33, with the gate insulating film 44 straddling between the emitter region 41 and the base surficial portion 40.

[0140] An interlayer insulating film 46 composed of SiO.sub.2 is layered on the SiC base layer 33 in a manner covering the gate electrode 45.

[0141] The interlayer insulating film 46 is formed with contact holes 47 and 48 penetrating through the interlayer insulating film 46 in the thickness direction directly above the emitter region 41 and the base surficial portion 40 respectively.

[0142] The emitter electrode 26 penetrates collectively into the contact holes 47 and 48 in a manner covering the interlayer insulating film 46 and is connected to the emitter region 41, the channel contact region 43, and the base surficial portion 40 through the contact holes 47 and 48. The emitter electrode 26 is an AlCu electrode. Accordingly, the emitter electrode 26 includes an ohmic contact portion 49 in ohmic contact with the n.sup.+-type emitter region 41 and the p.sup.+-type channel contact region 43, which have a high impurity concentration, and a Schottky joint portion 50 forming a Schottky junction with the n.sup.+-type SiC base layer 33, which has a low impurity concentration.

[0143] As described heretofore, the semiconductor chip 8 is formed with the vertical IGBT 9 including the emitter electrode 26, the emitter region 41 connected to the emitter electrode 26, the channel region 39 formed in a manner contacting the side of the emitter region 41 nearer the second surface 25 of the SiC semiconductor layer 23, the SiC base layer 33 formed in a manner contacting the side of the channel region 39 nearer the second surface 25 of the SiC semiconductor layer 23, the collector regions 37 formed in a manner contacting the side of the SiC base layer 33 nearer the second surface 25 of the SiC semiconductor layer 23, and the collector electrode 27 connected to the collector regions 37.

[0144] The emitter electrode 26 and the collector electrode 27 of the IGBT 9 are then shared between the MOSFET 11 and the Schottky barrier diode 12, and the MOSFET 11 also includes the emitter region 41 (source region 42), the channel region 39, the SiC base layer 33, and the SiC substrate 32 as impurity regions connected to these electrodes. The Schottky barrier diode 12 also includes the SiC base layer 33 and the SiC substrate 32 as impurity regions connected to the electrodes 26 and 27.

[0145] That is, in the semiconductor chip 8, the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12 are integrated into a single unit cell.

[0146] The MOSFET 11 incorporates a pn diode (body diode 10) defined by a pn junction between the p-type channel region 39 and the n.sup.-type SiC base layer 33, where the p-side (anode side) of the body diode 10 is connected with the anode electrode 30 and the emitter electrode 26, while the n-side (cathode side) is connected with the cathode electrode 31 and the collector electrode 27.

[0147] Thus, the three devices, IGBT 9, MOSFET 11 incorporating the body diode 10, and Schottky barrier diode 12, are collectively mounted on the semiconductor chip 8 and connected in parallel to each other.

[0148] FIGS. 4A to 4F show sequential steps of a process for manufacturing the semiconductor chip 8 shown in FIG. 3.

[0149] In order to manufacture the semiconductor chip 8, an epitaxial growth method such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy), or MBE (Molecular Beam Epitaxy) is used to grow an SiC crystal while doping n-type impurities into a surface of the wafer SiC substrate 32 as shown in FIG. 4A. This causes the n.sup.-type SiC base layer 33 to be formed on the SiC substrate 32.

[0150] Next, as shown in FIG. 4B, a hard mask 51 is formed and patterned on the second surface 25 of the SiC substrate 32 and then dry-etched at least until the SiC base layer 33 is exposed on the second surface 25 of the SiC substrate 32. This causes the SiC substrate 32 to be selectively dug from the second surface 25 and thereby the trenches 36 to be formed.

[0151] Next, as shown in FIG. 4C, with the hard mask 51 used to form the trenches 36 being left, p-type impurities are accelerated toward the trenches 36 exposed through the hard mask 51 to be implanted into the bottom surfaces of the trenches 36 (ion implantation). Next, the SiC base layer 33 is annealed. This causes the p-type impurities implanted into the bottom surfaces of the trenches 36 to be activated and thereby the collector regions 37 to be formed in the SiC base layer 33. Thereafter, the hard mask 51 is peeled off.

[0152] Next, as shown in FIG. 4D, hard mask formation and ion implantation are conducted according to the shapes of the channel region 39, the emitter region 41, and the channel contact region 43 as well as the types of impurities, and then the SiC base layer 33 is annealed in a similar manner as in the step shown in FIG. 4C. This causes the n-type impurities and the p-type impurities implanted into the SiC base layer 33 to be activated and thereby the channel region 39, the emitter region 41, and the channel contact region 43 to be simultaneously formed in the SiC base layer 33.

[0153] Next, as shown in FIG. 4E, a thermal oxidation method, for example, is used to form the gate insulating film 44 on the first surface 24 of the SiC base layer 33. Subsequently, a CVD technique, for example, is used to deposit polysilicon over the SiC base layer 33. The deposited polysilicon is then patterned to form the gate electrode 45.

[0154] Next, a CVD method, for example, is used to layer the interlayer insulating film 46 on the SiC base layer 33. Subsequently, the interlayer insulating film 46 and the gate insulating film 44 are selectively dry-etched to form the contact holes 47 and 48 simultaneously.

[0155] Next, as shown in FIG. 4F, a sputtering method, for example, is used to deposit AlCu on the interlayer insulating film 46 in a manner filling the contact holes 47 and 48. This causes the emitter electrode 26 to be formed. Thereafter, the metal silicide 38 is formed on the inner surfaces of the trenches 36, and then a sputtering method, for example, is used to deposit AlCu on the second surface 25 of the SiC substrate 32 in a manner filling the inside of the metal silicide 38. This causes the collector electrode 27 to be formed.

[0156] The semiconductor chip 8 shown in FIG. 3 is thus formed through the foregoing steps.

[0157] In the IGBT 9 mounted on the semiconductor package 1, holes are injected from the p.sup.+-type collector regions 37 to the n.sup.-type SiC base layer 33 to cause a conductivity modulation in the SiC base layer 33, whereby the on-resistance of the SiC base layer 33 (drift layer) can be reduced. For this reason, even if the SiC base layer 33 may have a low impurity concentration and/or an increased thickness and therefore a high original resistance to increase the voltage resistance of the IGBT 9, the on-resistance can be maintained sufficiently low. As a result, the IGBT 9 is more useful as a device for use in a high-voltage range than an SiC-MOSFET.

[0158] Meanwhile, since SiC has a pn barrier higher than that of Si, a high on-voltage is required to use the IGBT in a low-current range (e.g., of 4 A or lower). This is a very high value even in comparison with the SiC-MOSFET. Unlike the IGBT, the SiC-MOSFET, which uses SiC, undergoes a linear increase in the on-current from the initial stage, which is not particularly disadvantageous in the low-current range. For use in a current range of around 1 A, for example, the SiC-MOSFET has an on-voltage of about 0.8 V and the Si-IGBT has an on-voltage of about 1.3 V, while the SiC-IGBT has an on-voltage of 3.5 V, that is, there is a difference of about four times.

[0159] Hence, in accordance with the semiconductor package 1, the MOSFET 11 is connected in parallel to the IGBT 9. This allows a current to flow through the semiconductor package 1 by turning on the IGBT 9 or the MOSFET 11. Accordingly, for use in a low-current range, the semiconductor package 1 can be operated with the on-voltage of the MOSFET 11, whereby the on-voltage in the low-current range can be reduced.

[0160] Also, in this preferred embodiment, the IGBT 9, the MOSFET 11 incorporating the body diode 10, and the Schottky barrier diode 12 are integrated into a single unit cell in the semiconductor chip 8. As a result, the semiconductor package 1 can be reduced in size and thereby the capacitance between the devices can be reduced.

[0161] On the other hand, the IGBT 9, in which the cathode of the pn diode defined by the pn junction between the p-type channel region 39 and the n.sup.-type SiC base layer 33 is connected to the cathode of the pn diode defined by the pn junction between the p.sup.+-type collector regions 37 and the n.sup.-type SiC base layer 33, cannot incorporate a body diode 10 like the MOSFET 11. It is therefore difficult to consume a back electromotive force if occurring to the load.

[0162] Hence, in accordance with the semiconductor package 1, the MOSFET 11 incorporates the body diode 10 and the body diode 10 is connected in parallel to the IGBT 9. Accordingly, even if a back electromotive force may occur to the load, the rectification behavior of the body diode 10 causes a current due to the back electromotive force to flow through the load as a reflux current, which can prevent such a high back electromotive force from being applied to the IGBT 9.

[0163] Further, since the Schottky barrier diode 12 is connected in parallel to the IGBT 9, the recovery time can be shortened, whereby the semiconductor package 1 can achieve fast recovery.

[0164] In addition, since the IGBT 9 and the MOSFET 11 are integrated into the same semiconductor chip 8, the collector regions 37 and the drain region 34, which are selectively exposed on the second surface 25 of the SiC semiconductor layer 23, can be formed utilizing a known semiconductor device manufacturing technique including etching of the SiC substrate 32 and impurity implantation into the SiC base layer 33 as shown in FIG. 4A to 4C. The collector regions 37 and the drain region 34 can thus be formed easily at the second surface 25 of the SiC semiconductor layer 23.

[0165] In addition, the deepest portions of the trenches 36 are not required to be positioned at the interface between the SiC substrate 32 and the SiC base layer 33 as shown in FIG. 3, but may be, for example, at a position nearer the first surface 24 of the SiC base layer 33 with respect to the interface as shown in FIG. 5. In this case, the bottom surface and a portion of the side surface of each trench 36 is to be defined by the SiC base layer 33, while the rest of the side surface is to be defined by the SiC substrate 32. Alternatively, the deepest portions may be at a position nearer the second surface 25 of the SiC substrate 32 with respect to the interface as shown in FIG. 6. In this case, the bottom surface and the side surface of each trench 36 are to be defined by the SiC substrate 32.

[0166] Further, the gate electrode 45 may be formed straddling between adjacent channel regions 39 in a manner covering the base surficial portion 40 as shown in FIG. 7, for example. In this case, since the base surficial portion 40 is not exposed and cannot be connected with the emitter electrode 26 (Schottky joint portion 50), the Schottky barrier diode 12 is not to be provided.

[0167] Furthermore, the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12 may be formed as separate unit cells in the SiC semiconductor layer 23.

[0168] The semiconductor package 1 may be built and used in an inverter circuit as shown in FIG. 8, for example. In addition, in FIG. 8, the IGBT 9 and the MOSFET 11 are integrated into a single transistor for the purpose of easy illustration.

[0169] The inverter circuit 58 is a three-phase inverter circuit connected to a three-phase motor 59, including a DC power supply 60 and a switching portion 61.

[0170] A high-voltage wire 62 and a low-voltage wire 63 are connected, respectively, to the high-voltage and low-voltage sides of the DC power supply 60.

[0171] The switching portion 61 includes three series circuits 64 to 66 corresponding, respectively, to the U-phase 59U, V-phase 59V, and W-phase 59W of the three-phase motor 59.

[0172] The series circuits 64 to 66 are connected in parallel between the high-voltage wire 62 and the low-voltage wire 63. The series circuits 64 to 66 include high-side transistors (IGBT 9+MOSFET 11) 67H to 69H on the high-voltage side and low-side transistors (IGBT 9+MOSFET 11) 67L to 69L on the low-voltage side respectively. Regenerative diodes 70H to 72H and 70L to 72L are connected in parallel to the respective transistors 67H to 69H and 67L to 69L such that the forward current flows from the low-voltage side to the high-voltage side.

[0173] A switching signal is input from a control circuit not shown to the gates of the transistors 67H to 69H and 67L to 69L. In response to the switching signal, the transistors 67H to 69H and 67L to 69L perform switching operations. This causes a three-phase AC current to flow through the three-phase motor 59 and drive the three-phase motor 59.

[0174] FIG. 9 is a schematic cross-sectional view of a semiconductor chip according to a second preferred embodiment of the present invention. In FIG. 9, portions corresponding to those shown in FIG. 3 are designated by the same reference signs to omit the description thereof.

[0175] In the semiconductor chip 71 shown in FIG. 9, the multiple trenches 36 are formed in a manner penetrating through the SiC substrate 32 into the SiC base layer 33. This causes a step 72 to be provided between the bottom surface of each trench 36 and the second surface of the SiC base layer 33. The second surface of the SiC base layer 33 selectively protrudes correspondingly to the steps 72 to form convex portions 73.

[0176] The SiC base layer 33 includes an n.sup.+-type buffer layer 74 formed in a manner surrounding the collector regions 37 and an n.sup.-type drift layer 75 formed on the buffer layer 74 to define the first surface 24 of the SiC semiconductor layer 23. The impurity concentration of the buffer layer 74 is higher than that of the drift layer 75. For example, the buffer layer 74 has an impurity concentration of 1.010.sup.18 to 1.010.sup.15 atoms.Math.cm.sup.3, while the drift layer 75 has an impurity concentration of 5.010.sup.16 to 1.010.sup.14 atoms.Math.cm.sup.3.

[0177] The buffer layer 74 includes first portions 76 protruding toward the second surface 25 of the SiC semiconductor layer 23 along the surfaces of the convex portions 73 and second portions 77 protruding in the opposite direction of the first portions 76 to surround the collector regions 37, the first and second portions formed in a switchback manner alternately according to the pitch P of the trenches 36.

[0178] The drift layer 75 constitutes a major portion of the SiC base layer 33 and is in contact with the channel region 39 at the first surface 24 of the SiC semiconductor layer 23.

[0179] A high-concentration impurity region 78 having an impurity concentration higher than that of the other portions of the SiC substrate 32 is formed in the vicinity of the first surface of the SiC substrate 32 (in the vicinity of the bottom of each trench 36). The high-concentration impurity region 78 is in contact with each convex portion 73 of the SiC base layer 33.

[0180] FIGS. 10A to 10H show sequential steps of a process for manufacturing the semiconductor chip shown in FIG. 9.

[0181] In order to manufacture the semiconductor chip 71, n-type impurities (e.g., P or As) are implanted into a surface of the wafer SiC substrate 32 to form the high-concentration impurity region 78 as shown in FIG. 10A.

[0182] Next, as shown in FIG. 10B, an epitaxial growth method such as CVD, LPE, or MBE is used to grow an SiC crystal while doping n-type impurities into the surface of the SiC substrate 32. This causes a first high-concentration impurity layer 79 as a base of the buffer layer 74 and the drift layer 75 to be formed in this order and thereby the n.sup.-type SiC base layer 33 to be formed on the SiC substrate 32.

[0183] Next, as shown in FIG. 10C, hard mask formation and ion implantation are conducted according to the shapes of the channel region 39, the emitter region 41, and the channel contact region 43 as well as the types of impurities. This causes the channel region 39, the emitter region 41, and the channel contact region 43 to be simultaneously formed in the SiC base layer 33.

[0184] Next, as shown in FIG. 10D, a hard mask 51 is formed and patterned on the second surface 25 of the SiC substrate 32 and then dry-etched at least until the drift layer 75 is exposed through the first high-concentration impurity layer 79 on the second surface 25 of the SiC substrate 32. This causes the SiC substrate 32 to be selectively dug from the second surface 25 and thereby the trenches 36 to be formed.

[0185] During this time, since the high-concentration impurity region 78 is formed in the vicinity of the first surface of the SiC substrate 32, when the etching face reaches the end (near the first surface) of the SiC substrate 32, another type of plasma can be detected different from that during etching of the other portions of the SiC substrate 32. As a result, the depth of the etching can be controlled precisely so as to penetrate through the first high-concentration impurity layer 79 to the extent possible.

[0186] Next, as shown in FIG. 10E, with the hard mask 51 used to form the trenches 36 being left, n-type impurities are accelerated toward the trenches 36 exposed through the hard mask 51 to be implanted into the bottom surfaces of the trenches 36. This causes a second high-concentration impurity layer 80 and the first high-concentration impurity layer 79 to be integrated and thereby the buffer layer 74 to be formed.

[0187] Next, as shown in FIG. 10F, p-type impurities are accelerated toward the trenches 36 exposed through the hard mask 51 to be implanted into the bottom surfaces of the trenches 36 (second portions 77 of the buffer layer 74). This causes the collector regions 37 to be formed in the SiC base layer 33. Thereafter, the hard mask 51 is peeled off and then the SiC base layer 33 is annealed. This causes the channel region 39, the emitter region 41, the channel contact region 43, the buffer layer 74, the n-type impurities and the p-type impurities implanted into the collector regions 37 to be activated.

[0188] Next, as shown in FIG. 10G, a thermal oxidation method, for example, is used to form the gate insulating film 44 on the first surface 24 of the SiC base layer 33. Subsequently, a CVD method, for example, is used to deposit polysilicon over the SiC base layer 33. The deposited polysilicon is then patterned to form the gate electrode 45.

[0189] Next, a CVD method, for example, is used to layer the interlayer insulating film 46 on the SiC base layer 33. Subsequently, the interlayer insulating film 46 and the gate insulating film 44 are selectively dry-etched to form the contact holes 47 and 48 simultaneously.

[0190] Next, as shown in FIG. 10H, a sputtering method, for example, is used to deposit AlCu on the interlayer insulating film 46 in a manner filling the contact holes 47 and 48. This causes the emitter electrode 26 to be formed. Thereafter, the metal silicide 38 is formed on the inner surfaces of the trenches 36, and then a sputtering method, for example, is used to deposit AlCu on the second surface 25 of the SiC substrate 32 in a manner filling the inside of the metal silicide 38. This causes the collector electrode 27 to be formed.

[0191] The semiconductor chip 71 shown in FIG. 9 is thus formed through the foregoing steps.

[0192] As described heretofore, the semiconductor chip 71 can also achieve the same operational advantages as the above-described semiconductor chip 8.

[0193] Further, in the semiconductor chip 71 with the buffer layer 74 formed therein, when the IGBT 9 is in an off-state, the buffer layer 74 can inhibit the extension of the depletion layer generated at the interface between the channel region 39 and the drift layer 75 and thus prevent punch-through. It is therefore possible to design the semiconductor chip 71 as a punch-through type device to thereby achieve a low on-resistance.

[0194] The semiconductor package 1 according to the present invention may also be embodied as shown in FIGS. 11 to 14. In addition, in FIGS. 11 to 14, portions corresponding to those shown in FIGS. 1 to 3 are designated by the same reference signs. The detailed description of the portions designated by the same reference signs will be omitted below.

(1) SiC Substrate Segmented Type (FIGS. 11 and 12)

[0195] For example, the SiC substrate 52 may be segmented into multiple portions such that p.sup.+-type portions 53 and n.sup.+-type portions 54 are arranged alternately in a striped manner and exposed on the second surface 25 of the SiC substrate 52 so that the p.sup.+-type portions 53 can be utilized as the collector regions 37 of the IGBT 9, while the n.sup.+-type portions 54 can be utilized as the drain region 34 of MOSFET 11.

[0196] Also in this SiC substrate segmented type, the SiC base layer 33 may have a bilayer structure including the buffer layer 74 and the drift layer 75 as shown in FIG. 12. In this case, the buffer layer 74 is formed in a manner covering the p.sup.+-type portions 53 and the n.sup.+-type portions 54 collectively along the first surface of the SiC substrate 32.

(2) Trench-Gate Type (FIG. 13)

[0197] The IGBT 9 may be, for example, a trench-gate type, although it is a planar-gate type in the above-described preferred embodiments.

[0198] In the trench-gate type IGBT 9, a gate trench 55 is formed in a central portion of the channel region 39, the gate trench 55 penetrating from the first surface 24 of the SiC base layer 33 through the emitter region 41 and the channel region 39 to reach the SiC base layer 33 at the deepest portion.

[0199] A gate insulating film 56 composed of SiO.sub.2 is formed in a manner covering the entire inner surface of the gate trench 55. The inside of the gate insulating film 56 is then filled with polysilicon, so that a gate electrode 57 is embedded in the gate trench 55.

[0200] The channel contact region 43 is formed in a peripheral portion surrounding the central portion of the channel region 39 in a manner penetrating from the first surface 24 of the SiC base layer 33 through a peripheral portion of the emitter region 41 to reach the channel region 39.

(3) Device Separated Type (FIG. 14)

[0201] The IGBT 9, the MOSFET 11, and the Schottky barrier diode 12 may be formed separately and respectively as an IGBT chip 15, a MOSFET chip 16, and a Schottky barrier diode chip 17, although they are integrated into the same semiconductor chip 8 in the above-described preferred embodiments.

[0202] In this case, the MOSFET chip 16 and the Schottky barrier diode chip 17 may be formed using not SiC but another semiconductor material such as Si, GaN, or GaAs.

[0203] The semiconductor chip according to the present invention may also be implemented in the following seventh to ninth preferred embodiments.

[0204] FIG. 15 is a schematic plan view of a semiconductor chip 101 according to a seventh preferred embodiment of the present invention. FIG. 16 is a schematic bottom view of the semiconductor chip 101 shown in FIG. 15. FIG. 17 shows an exemplary variation about the stripe direction of the collector region 109 shown in FIG. 16. FIG. 18 is a schematic cross-sectional view of the semiconductor chip 101 according to the seventh preferred embodiment of the present invention.

[0205] The semiconductor chip 101 has, for example, a square chip shape in a plan view. The chip-shaped semiconductor chip 101 has vertical and horizontal lengths of several millimeters on the paper surfaces of FIGS. 15 and 16.

[0206] The semiconductor chip 101 includes an n.sup.+-type SiC substrate 102 and an n.sup.-type SiC base layer 103 formed on the SiC substrate 102. The n.sup.+-type SiC substrate 102 defines a drain region 104 of the MOSFET 11 and a cathode region 105 of the Schottky barrier diode 12. The SiC base layer 103 serves as a drift region 116 in the MOSFET 11 and the Schottky barrier diode 12.

[0207] Multiple second surface trenches 106 are formed in a manner penetrating from the second surface of the SiC substrate 102 through the SiC substrate 102 into the SiC base layer 103. This causes a step 107 to be provided between the bottom surface of each second surface trench 106 and the second surface of the SiC base layer 103. The second surface of the SiC base layer 103 selectively protrudes correspondingly to the steps 107 to form convex portions 108.

[0208] The multiple second surface trenches 106 are formed in, for example, a striped manner at regular intervals. In addition, the trenches may be formed in, for example, a grid manner without limiting to the striped manner. In the case of a striped manner, the stripe direction may be parallel with the direction of first surface trenches 131 (to be described hereinafter) as shown in FIG. 16 or may intersect with the direction of the first surface trenches 131 (to be described hereinafter) as shown in FIG. 17.

[0209] The side surface of each second surface trench 106 is defined by the SiC substrate 102, while the bottom surface is defined by the SiC base layer 103. P.sup.+-type collector regions 109 (collector regions 109 of the IGBT 9) are formed on the bottom surface (second surface portion of the SiC base layer 103).

[0210] A collector electrode 110 is then formed in a manner covering the entire second surface of the SiC substrate 102. The collector electrode 110 penetrates collectively into all the second surface trenches 106 and is connected to the SiC substrate 102 via the side surface of each second surface trench 106, while connected to the collector regions 109 via the bottom surfaces of the respective second surface trenches 106. The collector electrode 110 is an AlCu electrode with a metal silicide 111 formed in a manner contacting the inner surface (side surface and bottom surface) of each second surface trench 106. This can bring the collector electrode 110 into ohmic contact with any target of whichever conductive type including the n.sup.+-type SiC substrate 102 and the p.sup.+-type collector regions 109.

[0211] The collector electrode 110 is an external electrode common to the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12. In the MOSFET 11, the collector electrode 110 serves as a drain electrode 112. On the other hand, in the Schottky barrier diode 12, the collector electrode 110 serves as a cathode electrode 113.

[0212] A high-concentration impurity region 114 having an impurity concentration higher than that of the other portions of the SiC substrate 102 is formed in the vicinity of the first surface of the SiC substrate 102 (in the vicinity of the bottom of each second surface trench 106). The high-concentration impurity region 114 is in contact with each convex portion 108 of the SiC base layer 103.

[0213] The SiC base layer 103 includes a buffer region 115 and a drift region 116.

[0214] The buffer region 115 includes first portions 117 protruding toward the second surface of the SiC base layer 103 along the surfaces of the convex portions 108 and second portions 118 protruding in the opposite direction of the first portions 117 to surround the collector regions 109, the first and second portions formed in a switchback manner alternately according to the pitch of the second surface trenches 106.

[0215] The drift region 116 has a trilayer structure including a base drift region 125, a low-resistance drift region 126, and a surficial drift region 127, where the base drift region 125 is in contact with the buffer region 115 and the surficial drift region 127 is exposed on the first surface of the SiC base layer 103.

[0216] A P-type channel region 119 is selectively formed in a surficial portion of the drift region 116, and an n.sup.+-type emitter region 120 is formed in a surficial portion of the channel region 119. The emitter region 120 is exposed on the first surface of the SiC base layer 103 to define a portion of the first surface. The emitter region 120 serves also as a source region 121 of the MOSFET 11.

[0217] The emitter region 120 and the channel region 119 constitute a unit cell of the IGBT 9 (MOSFET 11). Between adjacent unit cells of the IGBT 9 (MOSFET 11), the drift region 116 is partially exposed on the first surface of the SiC base layer 103.

[0218] A gate trench 122 is formed in the SiC base layer 103, the gate trench penetrating from the first surface of the SiC base layer 103 through the emitter region 120 and the channel region 119 to reach an intermediate portion of the low-resistance drift region 126 at the deepest portion. This causes the emitter region 120 (source region 121) to define a portion of the side surface of the gate trench 122. The channel region 119 similarly defines a portion of the side surface of the gate trench 122. The drift region 116 defines a portion of the side surface and the bottom surface of the gate trench 122.

[0219] A gate insulating film 123 composed of an insulator such as SiO.sub.2 is formed in a manner covering the entire inner surface (side surface and bottom surface) of the gate trench 122. A gate electrode 124 composed of a conductor such as polysilicon is then embedded in the gate trench 122. The gate electrode 124 is opposed to the emitter region 120 (source region 121), the channel region 119, and the drift region 116 via the gate insulating film 123.

[0220] A field insulating film 128 composed of an insulator such as SiO.sub.2 is formed on the first surface of the SiC base layer 103. The field insulating film 128 has a contact hole through which the SiC base layer 103 is partially exposed as an active region 129 and covers a field region 130 that surrounds the active region 129.

[0221] Between adjacent unit cells of the IGBT 9 (MOSFET 11) in the active region 129, a first surface trench 131 is formed penetrating from the first surface of the SiC base layer 103 through the surficial drift region 127 to reach an intermediate portion of the low-resistance drift region 126 at the deepest portion. The first surface trench 131 is formed to have the same depth and shape as the gate trench 122.

[0222] The gate trench 122 and the first surface trench 131 may be formed in a striped manner parallel with (see FIG. 16) or intersecting with (e.g., perpendicular to) (see FIG. 17) the direction of the second surface trenches 106.

[0223] The gate trench 122 and the first surface trench 131 are defined by a bottom surface parallel with the first surface of the SiC base layer 103 and a side surface inclined with respect to the bottom surface. The inclination angle of the side surface is, for example, 90 degrees to 135 degrees. The depth of the first surface trench 131 (distance from the first surface of the SiC base layer 103 to the bottom surface of the first surface trench 131) is, for example, 3000 to 15000 . The width of the first surface trench 131 perpendicular to the longitudinal direction (at the deepest portion) is 0.3 m to 10 m.

[0224] The specific shape of the gate trench 122 and the first surface trench 131 may be a U-shaped trench having an inclination angle of about 90 degrees and a U-shaped bottom portion in a cross-sectional view, in which the edge portion of the bottom surface is curved outward so that the side surface and the bottom surface are connected via the curved surface as exemplified in FIG. 18, however, it is not limited thereto, the side surface and the bottom surface may be connected via an angular surface, for example.

[0225] The gate trench 122 and the first surface trench 131 may also be formed in, for example, an inverted trapezoidal trench having an inclination angle of greater than 90 degrees in a cross-sectional view taken along the width direction perpendicular to the longitudinal direction. In the inverted trapezoidal trench, the side surface may be entirely inclined at an inclination angle of greater than 90 degrees or a portion (lower portion) of the side surface may be selectively inclined at an inclination angle of greater than 90 degrees, while the other portions (upper portion) of the side surface may be formed at 90 degrees with respect to the bottom surface.

[0226] On the bottom surface and the side surface of the first surface trench 131, a p-type layer 132 serving as an electric field relaxing portion is formed along the inner surface of the first surface trench 131. The p-type layer 132 is formed from the bottom surface of the first surface trench 131 through the edge portion to the opening end of the first surface trench 131 in a manner covering both the channel region 119 and the emitter region 120 (source region 121).

[0227] The p-type layer 132 also forms a pn junction with the n-type SiC base layer 103. This causes the Schottky barrier diode 12 to be connected in parallel to the pn diode 133 constituted by the p-type layer 132 and the n-type SiC base layer 103 (low-resistance drift region 126).

[0228] In the p-type layer 132, a p.sup.+-type contact layer 134 is formed on a portion of the bottom surface of the first surface trench 131. The contact layer 134 is formed linearly in the longitudinal direction of the first surface trench 131 and has a depth (e.g., 0.05 m to 0.2 m) from the bottom surface of the first surface trench 131 to an intermediate portion of the p-type layer 132 in the depth direction.

[0229] On the other hand, an annular trench 135 penetrating from the first surface of the field region 130 through the surficial drift region 127 to reach an intermediate portion of the low-resistance drift region 126 at the deepest portion is formed in the field region 130. The annular trench 135 is formed in a manner surrounding the active region 129.

[0230] On the bottom surface and the side surface of the annular trench 135, a guard ring 136 is formed along the inner surface of the annular trench 135 in a manner exposed on the inner surface. The guard ring 136 is formed in the same step as the p-type layer 132 and has the same impurity concentration and thickness as the p-type layer 132.

[0231] An emitter electrode 137 composed of AlCu is formed on the field insulating film 128. The emitter electrode 137 is connected to the emitter region 120 (source region 121), the surficial drift region 127, and the contact layer 134 within the contact hole of the field insulating film 128.

[0232] That is, the emitter electrode 137 is an external electrode common to the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12. In the MOSFET 11, the emitter electrode 137 serves as a source electrode 138. On the other hand, in the Schottky barrier diode 12, the emitter electrode 137 serves as an anode electrode 139.

[0233] Accordingly, the emitter electrode 137 includes an ohmic contact portion 140 in ohmic contact with the n.sup.+-type emitter region 120 and the p.sup.+-type contact layer 134, which have a high impurity concentration, and a Schottky joint portion 141 forming a Schottky junction with the n.sup.-type surficial drift region 127, which has a low impurity concentration.

[0234] A surface protection film 142 composed of an insulator such as SiN is formed on the uppermost surface of the semiconductor chip 101. In a central portion of the surface protection film 142, an opening is formed through which the emitter electrode 137 is exposed. The bonding wire 14 shown in FIG. 1 is bonded to the emitter electrode 137 through the opening.

[0235] As described heretofore, the semiconductor chip 101 is formed with the vertical IGBT 9 including the emitter electrode 137, the emitter region 120 connected to the emitter electrode 137, the channel region 119 formed in a manner contacting the side of the emitter region 120 nearer the second surface of the SiC base layer 103, the drift region 116 formed in a manner contacting the side of the channel region 119 nearer the second surface of the SiC base layer 103, the collector region 109 formed in a manner contacting the side of the drift region 116 nearer the second surface of the SiC base layer 103, and the collector electrode 110 connected to the collector region 109.

[0236] The emitter electrode 137 and the collector electrode 110 of the IGBT 9 are then shared between the MOSFET 11 and the Schottky barrier diode 12, and the MOSFET 11 also includes the emitter region 120 (source region 121), the channel region 119, the drift region 116, and the drain region 104 as impurity regions connected to these electrodes. The Schottky barrier diode 12 also includes the drift region 116 and the cathode region 105 as impurity regions connected to these electrodes.

[0237] That is, in the semiconductor chip 101, the IGBT 9, the MOSFET 11, and the Schottky barrier diode 12 are integrated into a single unit cell.

[0238] Thus, the three devices, IGBT 9, MOSFET 11, and Schottky barrier diode 12, are collectively mounted on the semiconductor chip 101 and connected in parallel to each other.

[0239] Next, the impurity concentration of the SiC substrate 102 and the SiC base layer 103 will be described with reference to FIG. 19.

[0240] FIG. 19 illustrates the impurity concentration of the SiC substrate 102 and the SiC base layer 103.

[0241] As shown in FIG. 19, the SiC substrate 102 and the SiC base layer 103 are each composed of n-type SiC containing n-type impurities. These satisfy the magnitude relationship of the impurity concentration: SiC substrate 102>buffer region 115>drift region 116.

[0242] The SiC substrate 102 has an approximately constant concentration of, for example, 510.sup.18 to 510.sup.19 cm.sup.3 in the thickness direction. The buffer region 115 has a constant concentration or a concentration reduced along the surface of, for example, 110.sup.17 to 510.sup.18 cm.sup.3 in the thickness direction.

[0243] The concentration of the drift region 116 shows stepwise changes at the interfaces of the base drift region 125, the low-resistance drift region 126, and the surficial drift region 127. That is, with respect to each interface, there is a concentration difference between the layer nearer the first surface and the layer nearer the second surface.

[0244] The base drift region 125 has a constant concentration of, for example, 510.sup.14 to 510.sup.16 cm.sup.3 in the thickness direction. In addition, the concentration of the base drift region 125 may decrease from about 310.sup.16 cm.sup.3 to about 510.sup.15 cm.sup.3 continuously from the second surface toward the first surface of the SiC base layer 103 as indicated by the broken line in FIG. 19.

[0245] The low-resistance drift region 126 has a constant concentration higher than that of the base drift region 125, for example, 510.sup.15 to 510.sup.17 cm.sup.3 in the thickness direction. In addition, the concentration of the low-resistance drift region 126 may decrease from about 310.sup.17 cm.sup.3 to about 110.sup.16 cm.sup.3 continuously from the second surface toward the first surface of the SiC base layer 103 as indicated by the broken line in FIG. 19.

[0246] The surficial drift region 127 has a constant concentration lower than that of the base drift region 125 and the low-resistance drift region 126, for example, 510.sup.14 to 110.sup.16 cm.sup.3 in the thickness direction.

[0247] As shown in FIG. 18, since the Schottky barrier diode 12, which has a stripe-like unit cell (line cell) sandwiched between adjacent first surface trenches 131, has a current flow region (current path) limited by the distance between the adjacent first surface trenches 131, if the portions defining the unit cell in the SiC base layer 103 have a low impurity concentration, the unit cell may have a high resistance.

[0248] Hence, as shown in FIG. 19, the concentration of the low-resistance drift region 126 defining the base portion of the unit cell is set higher than that of the base drift region 125. Accordingly, even if the current path may be limited by the distance between the first surface trenches 131, the low-resistance drift region 126, which has the relatively high concentration, can suppress an increase in resistance of the unit cell. As a result, the unit cell can have a low resistance.

[0249] On the other hand, since the surficial drift region 127, which has the relatively low concentration, is provided in a surficial portion of the unit cell in contact with the emitter electrode 137 (anode electrode 139), the electric field intensity at the surface of the SiC base layer 103 upon reverse voltage application can be reduced. As a result, the reverse leakage current can be further reduced.

[0250] Next, a process for manufacturing the semiconductor chip 101 shown in FIG. 18 will be described.

[0251] FIGS. 20A to 20D show sequential steps of the process for manufacturing the semiconductor chip 101 shown in FIG. 18.

[0252] First, as shown in FIG. 20A, in accordance with the steps shown in FIGS. 10A and 10B, the high-concentration impurity region 114 is formed on a surface of the wafer SiC substrate 102, and then a first high-concentration impurity region 143 as a base of the buffer region 115 and the drift region 116 are epitaxially grown sequentially to form the n.sup.-type SiC base layer 103.

[0253] Next, as shown in FIG. 20B, in accordance with the step shown in FIG. 10C, hard mask formation and ion implantation are conducted according to the shapes of the channel region 119 and the emitter region 120 (source region 121) as well as the types of impurities. This causes the channel region 119 and the emitter region 120 (source region 121) to be formed in the SiC base layer 103.

[0254] Next, a hard mask is formed according to the patterns of the gate trench 122, the first surface trench 131, and the annular trench 135 and then, through etching using the hard mask, the gate trench 122, the first surface trench 131, and the annular trench 135 are simultaneously formed to have the same depth.

[0255] Next, impurities are selectively implanted into the inner surfaces of the first surface trench 131 and the annular trench 135 to form the p-type layer 132 and the guard ring 136 simultaneously. Further, impurities are selectively formed on the bottom surface of the first surface trench 131 to form the contact layer 134.

[0256] Next, as shown in FIG. 20C, in accordance with the step shown in FIG. 10D, a hard mask is formed and patterned on the second surface of the SiC substrate 102 and then dry-etched at least until the drift region 116 (base drift region 125) is exposed through the first high-concentration impurity region 143 on the second surface of the SiC substrate 102. This causes the SiC substrate 102 to be selectively dug from the second surface and thereby the second surface trenches 106 to be formed.

[0257] Next, as shown in FIG. 20D, in accordance with the step shown in FIG. 10E, n-type impurities are implanted into the bottom surfaces of the second surface trenches 106 to form the buffer region 115. Next, in accordance with the step shown in FIG. 10F, p-type impurities are implanted into the bottom surfaces of the second surface trenches 106 (second portions 118 of the buffer region 115) to form the collector regions 109 in the SiC base layer 103.

[0258] Thereafter, the SiC base layer 103 is annealed. This causes the n-type impurities and the p-type impurities implanted into the drift region 116, the channel region 119, the emitter region 120 (source region 121), the contact layer 134, the buffer region 115, and the collector regions 109 to be activated.

[0259] Subsequently, in accordance with the above-described method or a known semiconductor manufacturing technique, the gate insulating film 123, the gate electrode 124, the field insulating film 128, the emitter electrode 137, the collector electrode 110, etc., are formed to obtain the semiconductor chip 101 shown in FIG. 18.

[0260] As described heretofore, the semiconductor chip 101 can also achieve the same operational advantages as the above-described semiconductor chips 8 and 71.

[0261] Further, in accordance with the semiconductor chip 101, since the first surface trench 131 is formed adjacent to the Schottky joint portion 141, the electric field intensity at the Schottky interface between the SiC base layer 103 and the anode electrode 139 can be reduced. As a result, the barrier of the Schottky interface can be set low, whereby the Schottky barrier diode can have a low rise voltage.

[0262] Furthermore, since the p-type layer 132 is formed on the inner surface of the first surface trench 131, the reverse leakage current can be reduced in the entire semiconductor chip 101. That is, since the reverse leakage current can be reduced even if a reverse voltage close to the breakdown voltage may be applied, the voltage resistance characteristic of the SiC semiconductor can be efficiently utilized.

[0263] In addition, since the pn diode 133 is connected in parallel to the Schottky barrier diode 12, a surge current, if it may flow through the semiconductor chip 101, can partially flow through the incorporated pn diode 133. As a result, the surge current flowing through the Schottky barrier diode 12 can be reduced whereby thermal destruction of the Schottky barrier diode 12 due to surge current can be prevented.

[0264] Next, a semiconductor chip 151 according to an eighth preferred embodiment will be described.

[0265] FIG. 21 is a schematic cross-sectional view of the semiconductor chip 151 according to the eighth preferred embodiment of the present invention. In FIG. 21, portions corresponding to those shown in FIG. 18 are designated by the same reference signs to omit the description thereof.

[0266] In the semiconductor chip 101 according to the above-described seventh preferred embodiment, the multiple second surface trenches 106 are formed and disposed in a striped manner in the active region 129. On the other hand, in the semiconductor chip 151 according to the eighth preferred embodiment, a single second surface trench 152 is formed correspondingly to the multiple first surface trenches 131 formed in a striped manner. The second surface trench 152 is formed in the second surface of the SiC substrate 102 in a manner covering approximately the entire active region 129.

[0267] Drain regions 153 of the MOSFET 11 (cathode regions 154 of the Schottky barrier diode 12) and collector regions 155 of the IGBT 9 are formed alternately in a striped manner on the bottom surface of the second surface trench 152.

[0268] FIGS. 22A to 22D show sequential steps of a process for manufacturing the semiconductor chip 151 shown in FIG. 21.

[0269] First, as shown in FIG. 22A, in accordance with the step shown in FIG. 20A, the high-concentration impurity region 114 is formed on a surface of the wafer SiC substrate 102, and then a first high-concentration impurity region 143 as a base of the buffer region 115 and the drift region 116 are epitaxially grown sequentially to form the n.sup.-type SiC base layer 103.

[0270] Next, as shown in FIG. 22B, in accordance with the step shown in FIG. 20B, hard mask formation and ion implantation are conducted according to the shapes of the channel region 119 and the emitter region 120 (source region 121) as well as the types of impurities. This causes the channel region 119 and the emitter region 120 (source region 121) to be formed in the SiC base layer 103.

[0271] Next, a hard mask is formed according to the patterns of the gate trench 122, the first surface trench 131, and the annular trench 135 and then, through etching using the hard mask, the gate trench 122, the first surface trench 131, and the annular trench 135 are simultaneously formed to have the same depth.

[0272] Next, impurities are selectively implanted into the inner surfaces of the first surface trench 131 and the annular trench 135 to form the p-type layer 132 and the guard ring 136 simultaneously. Further, impurities are selectively formed on the bottom surface of the first surface trench 131 to form the contact layer 134.

[0273] Next, as shown in FIG. 22C, in accordance with the step shown in FIG. 20C, a hard mask is formed and patterned on the second surface of the SiC substrate 102 and then dry-etched at least until the drift region 116 (base drift region 125) is exposed through the first high-concentration impurity region 143 on the second surface of the SiC substrate 102. This causes the SiC substrate 102 to be selectively dug from the second surface and thereby the second surface trench 152 to be formed.

[0274] Next, as shown in FIG. 22D, in accordance with the step shown in FIG. 20D, n-type impurities are implanted into the bottom surface of the second surface trench 152 to form the buffer region 115. Next, p-type impurities are implanted into the bottom surface of the second surface trench 152 to form the collector regions 155 in the SiC base layer 103. Further, n-type impurities are implanted into the bottom surface of the second surface trench 152 to form the drain regions 153 (cathode regions 154) in the SiC base layer 103.

[0275] Thereafter, the SiC base layer 103 is annealed. This causes the n-type impurities and the p-type impurities implanted into the drift region 116, the channel region 119, the emitter region 120 (source region 121), the contact layer 134, the buffer region 115, the collector regions 155, and the drain regions 153 (cathode regions 154) to be activated.

[0276] Subsequently, in accordance with the above-described method or a known semiconductor manufacturing technique, the gate insulating film 123, the gate electrode 124, the field insulating film 128, the emitter electrode 137, the collector electrode 110, etc., are formed to obtain the semiconductor chip 151 shown in FIG. 21.

[0277] As described heretofore, the semiconductor chip 151 can also achieve the same operational advantages as the above-described semiconductor chips 8, 71, and 101.

[0278] Next, a semiconductor chip 161 according to a ninth preferred embodiment will be described.

[0279] FIG. 23 is a schematic cross-sectional view of the semiconductor chip 161 according to the ninth preferred embodiment of the present invention. In FIG. 23, portions corresponding to those shown in FIG. 18 are designated by the same reference signs to omit the description thereof.

[0280] In the semiconductor chips 101 and 151 according to the above-described seventh and eighth preferred embodiments, the SiC substrate 102 is provided to support the SiC base layer 103 thereon. On the other hand, in the semiconductor chip 161 according to the ninth preferred embodiment, the SiC substrate 102 is not provided, so that the entire second surface of the SiC base layer 103 is exposed.

[0281] A buffer region 162 is formed over the entire second surface of the exposed SiC base layer 103. In the buffer region 162, drain regions 163 of the MOSFET 11 (cathode regions 164 of the Schottky barrier diode 12) and collector regions 165 of the IGBT 9 are formed alternately in a striped manner so as to be exposed on the second surface of the SiC base layer 103.

[0282] FIGS. 24A to 24F show sequential steps of a process for manufacturing the semiconductor chip 161 shown in FIG. 23.

[0283] First, as shown in FIG. 24A, only the base drift region 125 is epitaxially grown on a surface of a wafer substrate 166 to form the n.sup.-type SiC base layer 103. The substrate 166 used is not limited to an SiC substrate, but may adopt various substrates.

[0284] Next, as shown in FIG. 24B, a technique such as grinding, dry etching, or sand blasting is used to grind the substrate 166 until the second surface of the SiC base layer 103 is exposed to thereby remove the substrate 166.

[0285] Next, as shown in FIG. 24C, epitaxial growth or ion implantation is used to form the low-resistance drift region 126 and the surficial drift region 127 sequentially on the base drift region 125.

[0286] Next, as shown in FIG. 24D, n-type impurities are implanted into the entire second surface of the SiC base layer 103 to form the buffer region 162.

[0287] Next, as shown in FIG. 24E, in accordance with the step shown in FIG. 20B, hard mask formation and ion implantation are conducted according to the shapes of the channel region 119 and the emitter region 120 (source region 121) as well as the types of impurities. This causes the channel region 119 and the emitter region 120 (source region 121) to be formed in the SiC base layer 103.

[0288] Next, a hard mask is formed according to the patterns of the gate trench 122, the first surface trench 131, and the annular trench 135 and then, through etching using the hard mask, the gate trench 122, the first surface trench 131, and the annular trench 135 are simultaneously formed to have the same depth.

[0289] Next, impurities are selectively implanted into the inner surfaces of the first surface trench 131 and the annular trench 135 to form the p-type layer 132 and the guard ring 136 simultaneously. Further, impurities are selectively formed on the bottom surface of the first surface trench 131 to form the contact layer 134.

[0290] Next, as shown in FIG. 24F, in accordance with the step shown in FIG. 20D, p-type impurities are implanted into the second surface of the SiC base layer 103 to form the collector regions 65 in the SiC base layer 103. Further, n-type impurities are implanted into the second surface of the SiC base layer 103 to form the drain regions 163 (cathode regions 164) in the SiC base layer 103.

[0291] Thereafter, the SiC base layer 103 is annealed. This causes the n-type impurities and the p-type impurities implanted into the drift region 116, the channel region 119, the emitter region 120 (source region 121), the contact layer 134, the buffer region 162, the collector regions 165, and the drain regions 163 (cathode regions 164) to be activated.

[0292] Subsequently, in accordance with the above-described method or a known semiconductor manufacturing technique, the gate insulating film 123, the gate electrode 124, the field insulating film 128, the emitter electrode 137, the collector electrode 110, etc., are formed to obtain the semiconductor chip 161 shown in FIG. 23.

[0293] As described heretofore, the semiconductor chip 161 can also achieve the same operational advantages as the above-described semiconductor chips 8, 71, 101, and 151.

[0294] Although the preferred embodiments of the present invention have heretofore been described, the present invention can be embodied in still other forms.

[0295] For example, an arrangement may be adopted in which the conductive type of the semiconductor portions in the IGBT 9, the body diode 10, the MOSFET 11, and the Schottky barrier diode 12 is inverted. In the IGBT 9, for example, the p-type portions may be n-type, while the n-type portions may be p-type.

[0296] In the seventh to ninth preferred embodiments, the unit cells of the IGBT 9 and the MOSFET 11 and the unit cells of the Schottky barrier diode 12 are arranged alternately. However, the arrangement is not particularly limited, and two or more of the latter unit cells may be arranged between a pair of the former unit cells, for example.

[0297] The features understood from the disclosure of the above-described preferred embodiments may also be combined between different preferred embodiments. Further, the components presented in the preferred embodiments may be combined within the scope of the present invention.

[0298] The preferred embodiments of the present invention are merely specific examples used to clarify the technical contents of the present invention, and the present invention should not be understood as being limited to these specific examples, and the spirit and scope of the present invention is to be limited solely by the appended claims.

DESCRIPTION OF SIGNS

[0299] 1 Semiconductor package [0300] 2 Resin package [0301] 3 Gate terminal [0302] 4 Emitter terminal [0303] 5 Collector terminal [0304] 6 Island (of the collector terminal) [0305] 7 Terminal portion (of the collector terminal) [0306] 8 Semiconductor chip [0307] 9 IGBT [0308] 10 Body diode [0309] 11 MOSFET [0310] 12 Schottky barrier diode [0311] 13 Bonding wire [0312] 14 Bonding wire [0313] 15 IGBT chip [0314] 16 MOSFET chip [0315] 17 Schottky barrier diode chip [0316] 18 Bonding wire [0317] 19 Bonding wire [0318] 20 Bonding wire [0319] 21 Bonding wire [0320] 22 Bonding wire [0321] 23 SiC semiconductor layer [0322] 24 First surface (of the SiC semiconductor layer) [0323] 25 Second surface (of the SiC semiconductor layer) [0324] 26 Emitter electrode [0325] 27 Collector electrode [0326] 28 Source electrode [0327] 29 Drain electrode [0328] 30 Anode electrode [0329] 31 Cathode electrode [0330] 32 SiC substrate [0331] 33 SiC base layer [0332] 34 Drain region [0333] 35 Cathode region [0334] 36 Trench [0335] 37 Collector region [0336] 38 Metal silicide [0337] 39 Channel region [0338] 40 Base surficial portion [0339] 41 Emitter region [0340] 42 Source region [0341] 43 Channel contact region [0342] 44 Gate insulating film [0343] 45 Gate electrode [0344] 46 Interlayer insulating film [0345] 47 Contact hole [0346] 48 Contact hole [0347] 49 Ohmic contact portion [0348] 50 Schottky joint portion [0349] 51 Hard mask [0350] 52 SiC substrate [0351] 53 P.sup.+-type portion [0352] 54 N.sup.+-type portion [0353] 55 Gate trench [0354] 56 Gate insulating film [0355] 57 Gate electrode [0356] 58 Inverter circuit [0357] 59 Three-phase motor [0358] 59U U-phase (of the three-phase motor) [0359] 59V V-phase (of the three-phase motor) [0360] 59W W-phase (of the three-phase motor) [0361] 60 DC power supply [0362] 61 Switching unit [0363] 62 High-voltage wire [0364] 63 Low-voltage wire [0365] 64 Series circuit [0366] 65 Series circuit [0367] 66 Series circuit [0368] 67H High-side transistor [0369] 67L Low-side transistor [0370] 68H High-side transistor [0371] 68L Low-side transistor [0372] 69H High-side transistor [0373] 69L Low-side transistor [0374] 71 Semiconductor chip [0375] 72 Step [0376] 73 Convex portion [0377] 74 Buffer layer [0378] 75 Drift layer [0379] 76 First portion (of the buffer layer) [0380] 77 Second portion (of the buffer layer) [0381] 78 High-concentration impurity region [0382] 79 First high-concentration impurity layer [0383] 80 Second high-concentration impurity layer [0384] 101 Semiconductor chip [0385] 102 SiC substrate [0386] 103 SiC base layer [0387] 104 Drain region [0388] 105 Cathode region [0389] 106 Second surface trench [0390] 107 Step [0391] 108 Convex portion [0392] 109 Collector region [0393] 110 Collector electrode [0394] 111 Metal silicide [0395] 112 Drain electrode [0396] 113 Cathode electrode [0397] 114 High-concentration impurity region [0398] 115 Buffer region [0399] 116 Drift region [0400] 117 First portion (of the buffer region) [0401] 118 Second portion (of the buffer region) [0402] 119 Channel region [0403] 120 Emitter region [0404] 121 Source region [0405] 122 Gate trench [0406] 123 Gate insulating film [0407] 124 Gate electrode [0408] 125 Base drift region [0409] 126 Low-resistance drift region [0410] 127 Surficial drift region [0411] 128 Field insulating film [0412] 129 Active region [0413] 130 Field region [0414] 131 First surface trench [0415] 132 P-type layer [0416] 133 pn diode [0417] 134 Contact layer [0418] 135 Annular trench [0419] 136 Guard ring [0420] 137 Emitter electrode [0421] 138 Source electrode [0422] 139 Anode electrode [0423] 140 Ohmic contact portion [0424] 141 Schottky joint portion [0425] 142 Surface protection film [0426] 143 First high-concentration impurity region [0427] 151 Semiconductor chip [0428] 152 Second surface trench [0429] 153 Drain region [0430] 154 Cathode region [0431] 155 Collector region [0432] 161 Semiconductor chip [0433] 162 Buffer region [0434] 163 Drain region [0435] 164 Cathode region [0436] 165 Collector region [0437] 166 Substrate

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

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Cpc classification

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H01L2224/49113

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H01L25/18

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