As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.

Maintaining a synchronous replication relationship between two or more storage systems, including: receiving, by at least one of a plurality of storage systems across which a dataset will be synchronously replicated, timing information for at least one of the plurality of storage systems; and establishing, based on the timing information, a synchronous replication lease describing a period of time during which the synchronous replication relationship is valid, wherein a request to modify the dataset may only be acknowledged after a copy of the dataset has been modified on each of the storage systems.

A storage device includes a cell degradation measurement circuit configured to receive a cell degradation information request command that requests cell degradation information from a host, and provide first cell degradation information to the host in response to the cell degradation information request command, and a non-volatile memory including a plurality of memory cells. The cell degradation measurement circuit writes data to any one of the plurality of memory cells in response to the cell degradation information request command. The cell degradation measurement circuit reads the written data after a predetermined time has elapsed. The first cell degradation information is generated based on an error detection operation performed on the read data.

Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.

Disclosed is an operating method of a storage controller which communicates with a host and a non-volatile memory device. The method includes receiving a first request indicating a first zone of a plurality of zones from the host, setting a state of the first zone to an active state in response to the first request, assigning a first memory block of a plurality of memory blocks of the non-volatile memory device to the first zone updated to the active state, and storing user data corresponding to the first request in the first memory block. The first memory block is higher in reliability than a second memory block assigned to a second zone having a non-active state from among the plurality of zones, and the storage controller supports a zoned namespace (ZNS) standard of a NVM express.

Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.

Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.

An SPD-based memory monitoring and service life prediction method and system. Said method includes: acquiring parameter information of each memory bank in a server, and setting a weight for the parameter information; reading configuration information of each memory bank, and calculating occupation ratio information of parameters of each memory bank according to the configuration information and the parameter information; calculating state information of each memory bank according to the weight and the occupation ratio information; determining an influence factor according to the number of CPUs in the server and the number and position of memory banks in each CPU; and calculating a final memory state value according to the influence factor and the state information, and according to the used time and the state information of each memory bank, calculating the remaining service life of each memory bank by means of piecewise fitting using a least square method.

A storage appliance includes a first SSD, a second SSD, and a controller. The controller is able to calculate a first utilization parameter of the first SSD and a second utilization parameter of the second SSD. If the first utilization parameter is less than a threshold and the second utilization parameter exceeds the threshold, the controller identifies a data range stored on the first SSD to be removed. The removal of the data range from the first SSD causes the first utilization parameter to exceed the threshold. The controller then migrates the data range from the first SSD to the second SSD.