H01L27/1259

Display panel, manufacturing method thereof and display device
11710749 · 2023-07-25 · ·

Provided are a display panel, a manufacturing method thereof, and a display device. A first display region of the display panel includes first pixel units and first drive circuits, a second display region includes second pixel units and second drive circuits, wherein a pixel unit density of the first pixel units is less than a pixel unit density of the second pixel units, a number of first additional transistors in the first drive circuit is less than a number of second additional transistors in the second drive circuit, and an area of the orthographic projection of a channel area of the first drive transistor on the base substrate is less than an area of the orthographic projection of a channel area of the second drive transistor on the base substrate.

Semiconductor device including flip-flop circuit which includes transistors

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Method for manufacturing display panel, display panel, and display device
11561442 · 2023-01-24 · ·

This application discloses a method for manufacturing a display panel, a display panel, and a display device. The display panel has a display area and a peripheral area. The display panel includes a first substrate, a second substrate, a plurality of pixel elements, a plurality of data lines and scanning lines, and a plurality of color filters. The first substrate includes a first shading layer, the first shading layer being formed between two neighboring pixel elements to block the data lines or the scanning lines. The display area includes an opening area and a non-opening area, and the first shading layer is arranged only in the non-opening area. The second substrate includes a second shading layer arranged corresponding to the first shading layer. Each of the data lines and the scanning lines is blocked by at least one of the first shading layer and the second shading layer.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
20230230981 · 2023-07-20 ·

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including a first region and a second region that are adjacent to each other; an array structure, located on a surface of the substrate and on the first region; a conductive layer, located on a side of the array structure that is away from the substrate and electrically connected to the array structure; a wiring structure, located on a side of the conductive layer that is away from the array structure, where the wiring structure includes a re-wiring through hole, and the re-wiring through hole is electrically connected to the conductive layer; and a first dielectric layer, covering a surface of the second region of the substrate.

Array substrate and fabrication method thereof, display panel and display module

The present disclosure provides an array substrate and a fabrication method thereof, a display panel and a display module. The array substrate has a display region and a bonding region for bonding with a circuit board, and including: a data line and a gate line in the display region; and a bump unit in the bonding region. The bump unit includes: a gate line bump layer, which is in a same layer and made of a same material as the gate line, is connected to the data line, and includes a main body portion and a plurality of hollowed-out portions in the main body portion; and a data line bump layer, which is in a same layer and made of a same material as the data line, and covers the main body portion and the plurality of hollowed-out portions of the gate line bump layer.

Flexible array substrate, manufacturing method thereof, flexible display device

Embodiments of the present disclosure provide a flexible array substrate, a manufacturing method thereof, and a flexible display device, which relate to the field of display technology, and can reduce the difficulty of wiring, decrease the IR drop, and improve the problem that the wiring is prone to breakage when bent. The flexible array substrate includes a substrate, the substrate including a first sub-substrate and a second sub-substrate which are stacked, the second sub-substrate including at least one via hole; a wiring layer disposed between the first sub-substrate and the second sub-substrate; and a pixel array layer disposed on a side of the second sub-substrate facing away from the first sub-substrate; the wiring layer including a wiring, wherein the pixel array layer is electrically connected to the wiring through the at least one via hole.

METHOD OF FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE
20230230983 · 2023-07-20 ·

A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.

Display device and method for manufacturing same

Provided is a display device including a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate and spaced apart from the first electrode, a plurality of first sub-insulating layers extending in a first direction, disposed on the substrate and on the first and second electrodes, and arranged in a second direction crossing the first direction, and a plurality of light emitting elements disposed between the first sub-insulating layers and electrically connected to the first electrode and the second electrode.

Display substrate, manufacturing method thereof, display panel and display device

Disclosed are a display substrate, a manufacturing method thereof, a display panel and a display device. The display panel comprises: a base substrate provided with a first area and a second area which are not overlapped with each other; a low temperature poly-silicon transistor arranged in the first area, the low temperature poly-silicon transistor comprises a poly-silicon active layer; an oxide transistor arranged in the second area, the oxide transistor comprises a first gate electrode; the first gate electrode is arranged in a same layer as the poly-silicon active layer, and a material of the first gate electrode is heavily-doped poly-silicon.

Array substrate, display panel, and display device

The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes: a substrate; and a first conductive structure, an interlayer insulation layer, and a second conductive structure sequentially disposed on the substrate. The first conductive structure has a first connection portion, the second conductive structure has a second connection portion, and the first connection portion is electrically coupled to the second connection portion through a via penetrating through the interlayer insulation layer. At least one of the first connection portion and the second connection portion is provided with an opening, and an orthographic projection of the opening on the substrate does not overlap an orthographic projection of the via on the substrate.