A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

A parameter adjustment method includes an acquisition process and a parameter changing process. The acquisition process acquires, from an inspection apparatus configured to inspect a combined substrate in which the first substrate and the second substrate are bonded by the bonding apparatus, an inspection result indicating a direction and a degree of distortion occurring in the combined substrate. The parameter changing process changes at least one of multiple parameters including at least one of the gap, an attraction pressure of the first substrate by the first holder, an attraction pressure of the second substrate by the second holder or a pressing force on the first substrate by the striker, based on trend information indicating a tendency of a change in the direction and the degree of the distortion when each of the multiple parameters is changed and the inspection result acquired in the acquiring of the inspection result.

A semiconductor module bonding structure includes: a semiconductor module including a semiconductor element and a positive terminal which is a plate-shaped power terminal electrically connected to the semiconductor element; and a main P bus bar which is a bus bar including a plate-shaped bonding part bonded to the positive terminal of the semiconductor module. The positive terminal of the semiconductor module which is one of the positive terminal and the bonding part of the main P bus bar that has a relatively small thickness is configures to be wider than the bonding part which is the other having a relatively large thickness, and the positive terminal and the bonding part are bonded together by fusion welding in the state of being arranged so that the respective thickness directions of the positive terminal and the bonding part are orthogonal to each other.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Anodic bonding method are disclosed. In one embodiment, an anodic bonding method may include: (1) providing a first substrate (100) having a semiconductor material; (2) providing a second substrate (200) having a bondable passivation material and contact vias (210); (3) contacting the first substrate and the second substrate (100, 200); (4) providing a resistance layer (300, 220) on the second substrate (200); and (5) applying a potential between the resistance layer and the first substrate.

A semiconductor device comprising a first substrate (100) including silicon may include a bondable passivation (200) made of a bondable material, especially a glass material; at least one contact via (210) extending through the passivation and contacting a region of the first substrate (100); an interface (204) created by anodic bonding between the substrate including silicon and the bondable passivation (200), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation (200) and the substrate (100)