A semiconductor device includes a semiconductor substrate having first and second main surfaces that oppose each other in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer includes a first electrode layer on a side of the semiconductor substrate, a second electrode layer that faces the first electrode layer, a dielectric layer disposed between the electrode layers, and a first outer electrode electrically connected to the first electrode layer through an opening in the dielectric layer. An end portion of the dielectric layer on a side of the first region is in contact with the first electrode layer, and in the dielectric layer, a size of the end portion in the thickness direction is smaller than a size of an inter-electrode portion between the first and second electrode layers in the thickness direction.

A semiconductor device includes a semiconductor substrate having first and second main surfaces that oppose each other in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer includes a first electrode layer on a side of the semiconductor substrate, a second electrode layer that faces the first electrode layer, a dielectric layer disposed between the electrode layers, and a first outer electrode electrically connected to the first electrode layer through an opening in the dielectric layer. An end portion of the dielectric layer on a side of the first region is in contact with the first electrode layer, and in the dielectric layer, a size of the end portion in the thickness direction is smaller than a size of an inter-electrode portion between the first and second electrode layers in the thickness direction.

A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are provided and a plurality of internal electrodes are stacked with the dielectric layer interposed therebetween and external electrodes disposed outside the body and connected to the plurality of internal electrodes. The body includes a high resistance portion disposed in at least one region between the dielectric layer and the internal electrode and inside the dielectric layer and having electric resistance higher than electric resistance of the internal electrode, and the high resistance portion and the plurality of internal electrodes include the same metal component and the same metal oxide component.

A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are provided and a plurality of internal electrodes are stacked with the dielectric layer interposed therebetween and external electrodes disposed outside the body and connected to the plurality of internal electrodes. The body includes a high resistance portion disposed in at least one region between the dielectric layer and the internal electrode and inside the dielectric layer and having electric resistance higher than electric resistance of the internal electrode, and the high resistance portion and the plurality of internal electrodes include the same metal component and the same metal oxide component.

A manufacturing method for capacitor structure includes: forming a dielectric layer on a first electrode, wherein the dielectric layer includes metal oxide layers doped with preset oxides, and part of the preset oxide and a metal oxide share oxygen atoms; and forming a second electrode on the dielectric layer, wherein the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

A manufacturing method for capacitor structure includes: forming a dielectric layer on a first electrode, wherein the dielectric layer includes metal oxide layers doped with preset oxides, and part of the preset oxide and a metal oxide share oxygen atoms; and forming a second electrode on the dielectric layer, wherein the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

An integrated circuit device includes: a lower electrode disposed on a substrate; an insulating support pattern supporting the lower electrode; a dielectric film surrounding the lower electrode and the insulating support pattern; a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern and includes a zirconium oxide layer; and an upper electrode disposed adjacent the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.

An integrated circuit device includes: a lower electrode disposed on a substrate; an insulating support pattern supporting the lower electrode; a dielectric film surrounding the lower electrode and the insulating support pattern; a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern and includes a zirconium oxide layer; and an upper electrode disposed adjacent the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.

Provided are a dielectric, a device including the same, and a method of preparing the dielectric. The dielectric material includes a NaNbO.sub.3 ternary material including a perovskite phase with a Sm element substituted into a Na site such that the NaNbO.sub.3 ternary material has a permittivity of 600 or more at 1 kHz, and a temperature coefficient of capacitance (TCC) of about -15% to about 15% in a range of about -55° C. to about +200° C.

Provided are a dielectric, a device including the same, and a method of preparing the dielectric. The dielectric material includes a NaNbO.sub.3 ternary material including a perovskite phase with a Sm element substituted into a Na site such that the NaNbO.sub.3 ternary material has a permittivity of 600 or more at 1 kHz, and a temperature coefficient of capacitance (TCC) of about -15% to about 15% in a range of about -55° C. to about +200° C.