An array substrate and a display device are provided in embodiments of the present disclosure. The array substrate includes a base substrate, a buffer layer, an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source-drain electrode electrically conductive layer, a passivation layer, and a first light shielding layer. The first light shielding layer is disposed on a side of the passivation layer facing away from the interlayer insulating layer. An orthographic projection of the first light shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active layer on the base substrate, and the first light shielding layer is formed by a photoresist material.

The disclosure relates to an array substrate, a display panel, and a method of manufacturing the array substrate. The array substrate includes a substrate, and a non-organic membrane layer, a first organic layer, and a source/drain electrode layer which are sequentially disposed on the substrate. The substrate includes a display region. A first opening and a second opening are defined in the non-organic membrane layer and defined in the display region. The first organic layer fills the first opening. A thickness of the first organic layer is not greater than a depth of the first opening. The first organic layer does not fill the second opening. The source/drain electrode layer covers an inner wall of the second opening.

A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

A method is provided for manufacturing a thin film transistor (TFT) backplate that includes a switch TFT and a drive TFT. The method is conducted such that each of the switch TFT and the drive TFT manufactured therewith includes a source electrode/a drain electrode and a gate electrode, and also includes an etching stopper layer, a semiconductor layer, and gate isolation layer that are disposed between the source electrode/the drain electrode and the gate electrode to form a TFT structure. The gate isolation layers of the switch TFT and drive TFT are formed of different materials, such as SiOx and Al.sub.2O.sub.3, or SiOx and SiNx, or Al.sub.2O.sub.3 and a mixture of SiNx and SiOx, such that electrical properties of the switch TFT and the drive TFT are made different.

A display device includes a substrate including a first area, a second area, and a bending area. A plurality of first wires are positioned in the first area. A plurality of second wires are positioned in the second area. An insulating layer is positioned in the bending area. A plurality of connecting wires are disposed on the insulating layer. Each of the connecting wires is connected with at least one of the first wires and at least one of the second wires. Each of the connecting wires includes a first portion and a second portion alternatingly arranged along an extending direction of the connecting wires. A width of the first portion is wider than a width of the second portion in a direction perpendicular to the extending direction each of the connecting wires.

A COA substrate manufacturing method including: forming a TFT on a base substrate; forming a second insulation layer on the TFT; forming a color resist layer on the second insulation layer; forming a third insulation layer on the color resist layer; forming a through hole which exposes the drain electrode of the TFT; forming an ITO film layer on the third insulation layer; forming a photoresist layer on the ITO film layer; performing a light-shielding process to the photoresist layer on the vias-region ITO film layer and an exposure process to the photoresist layer on the non vias-region ITO film layer; developing the photoresist layer on the vias-region ITO and the non vias-region ITO film layers to obtain a photoresist layer plug covered on the vias-region ITO film layer. The photoresist is provided to fill the through hole so as to improve the quality of a display device.

A display device includes a base substrate; a pixel electrode on the base substrate; a first conductive bar which is adjacent to and separated from a first edge of the pixel electrode in a top plan view, the first conductive bar disposed in a same layer as the pixel electrode; and a common electrode which overlaps the pixel electrode. In the top plan view, the first conductive bar includes: a first body which lengthwise extends along the first edge of the pixel electrode and includes an edge which faces the first edge of the pixel electrode, and a first ridge pattern and a second ridge pattern each protruding from the edge of the first body and toward the pixel electrode, the first and second ridge patterns consecutively disposed along a lengthwise direction of the first body.

Provided are a display device its method of manufacturing. The device includes a base; first and second thin-film transistors (TFT) on the base, adjacent to each; an organic layer covering the first and second TFT, comprising a first and second opening overlapping the drain electrodes of the first and second TFT, respectively; a common electrode on the organic layer comprising a common electrode opening overlapping the first opening and another common electrode opening overlapping the second opening; an insulating layer on a bump spacer which is on the common electrode; a first and second pixel electrode on the insulating layer overlapping the common electrode and electrically connected to the first and second TFT, respectively, wherein a minimum distance between the bump spacer and the common electrode opening is substantially equal to a minimum distance between the bump spacer and the other common electrode opening.

Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.

A semiconductor device capable of retaining data for a long time is provided. A first transistor and a second transistor having different electrical characteristics from those of the first transistor are provided over the same layer without an increase in the number of manufacturing steps.