A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

A thyristor, in particular a phase control thyristor, is disclosed with comprises: a) a semiconductor slab, in particular a semiconductor wave or die, in which a thyristor structure is formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points P.sub.i in the cathode region, said points having point locations x.sub.i, with iε{1; . . . ; N}, e) the points P.sub.l defining a Delaunay triangulation comprising a plurality of triangles T.sub.j with jε{1; . . . ; M), wherein f) for a first subset of triangles T.sub.l with lεS.sub.1⊂{1; . . . ; M), g) with each triangle T.sub.l being characterized by a geometric quantity having values q.sub.T,l with lεS.sub.1⊂{1; . . . ; M), said geometric quantity having a mean value μ, and i) a coefficient of variation of the values q.sub.T,l with lεS.sub.1 is smaller than 0.1, preferably smaller than 0.05, and/or ii) an absolute value of a skewedness of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 5, preferably smaller than 1, and/or iii) a Kurtosis of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 20, preferably smaller than 10, and h) for a second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.T,m with mεS.sub.2 deviate from the mean value by more than a predetermined amount, in particular by more than 30%, (1) a quotient of a standard deviation of the quantities q.sub.T,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.T,l with lεS.sub.1 is less than 1 or less than 0.1, and/or a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than

Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.

A trenched, vertical MOS-gated switch is described that uses only three or four masking steps to fabricate. In one embodiment, one mask is used to form first trenches having a first depth, wherein the first trenches are filled with doped polysilicon to form gates to control the conduction of the switch. A second mask is used to form second trenches having a shallower second depth. The second trenches are filled with the same metal used to form the top source electrode and gate electrode. The metal filling the second trenches electrically contacts a top source layer and a body region. A third mask is used to etch the metal to define the source metal, the gate electrode, and floating rings in a termination region surrounding the active area of the switch. An additional mask may be used to form third trenches in the termination region that are deeper than the first trenches.

Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.

The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.

A method of manufacturing a semiconductor integrated circuit, includes: forming a first well region having a second conductivity type in an upper portion of a support layer having a first conductivity type; forming an oxide film on the first well region by a thermal oxidation method to decrease a concentration of impurities at an top surface of top surface side of the first well region; removing the oxide film; forming a second well region having the first conductivity type in an upper portion of the first well region; and merging a semiconductor element having a main electrode region having the second conductivity type in the second well region.

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.